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authorRichard Henderson <richard.henderson@linaro.org>2024-05-27 19:05:33 +0000
committerRichard Henderson <richard.henderson@linaro.org>2024-06-19 10:55:12 -0700
commit15750faa8ecd070cbc01bbd22db8c7a2b7e410e5 (patch)
tree07002f6cbc28b200b5d1564ad709b0af1f50c972 /tcg/loongarch64
parente78dc00f1dc2caa898262e87324a1c47afb96208 (diff)
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tcg/loongarch64: Support LASX in tcg_out_dupm_vec
Each element size has a different encoding, so code cannot be shared in the same way as with tcg_out_dup_vec. Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/loongarch64')
-rw-r--r--tcg/loongarch64/tcg-target.c.inc30
1 files changed, 24 insertions, 6 deletions
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index cc54bc4..1e721b8 100644
--- a/tcg/loongarch64/tcg-target.c.inc
+++ b/tcg/loongarch64/tcg-target.c.inc
@@ -1690,8 +1690,10 @@ static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,
TCGReg r, TCGReg base, intptr_t offset)
{
- /* Handle imm overflow and division (vldrepl.d imm is divided by 8) */
- if (offset < -0x800 || offset > 0x7ff || \
+ bool lasx = type == TCG_TYPE_V256;
+
+ /* Handle imm overflow and division (vldrepl.d imm is divided by 8). */
+ if (offset < -0x800 || offset > 0x7ff ||
(offset & ((1 << vece) - 1)) != 0) {
tcg_out_addi(s, TCG_TYPE_I64, TCG_REG_TMP0, base, offset);
base = TCG_REG_TMP0;
@@ -1701,16 +1703,32 @@ static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,
switch (vece) {
case MO_8:
- tcg_out_opc_vldrepl_b(s, r, base, offset);
+ if (lasx) {
+ tcg_out_opc_xvldrepl_b(s, r, base, offset);
+ } else {
+ tcg_out_opc_vldrepl_b(s, r, base, offset);
+ }
break;
case MO_16:
- tcg_out_opc_vldrepl_h(s, r, base, offset);
+ if (lasx) {
+ tcg_out_opc_xvldrepl_h(s, r, base, offset);
+ } else {
+ tcg_out_opc_vldrepl_h(s, r, base, offset);
+ }
break;
case MO_32:
- tcg_out_opc_vldrepl_w(s, r, base, offset);
+ if (lasx) {
+ tcg_out_opc_xvldrepl_w(s, r, base, offset);
+ } else {
+ tcg_out_opc_vldrepl_w(s, r, base, offset);
+ }
break;
case MO_64:
- tcg_out_opc_vldrepl_d(s, r, base, offset);
+ if (lasx) {
+ tcg_out_opc_xvldrepl_d(s, r, base, offset);
+ } else {
+ tcg_out_opc_vldrepl_d(s, r, base, offset);
+ }
break;
default:
g_assert_not_reached();