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Author
Files
Lines
2023-02-27
target/i386: Fix BZHI instruction
Richard Henderson
1
-7
/
+7
2023-02-24
Merge tag 'pull-error-2023-02-23' of https://repo.or.cz/qemu/armbru into staging
Peter Maydell
3
-3
/
+0
2023-02-24
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
Peter Maydell
2
-1
/
+5
2023-02-23
error: Drop superfluous #include "qapi/qmp/qerror.h"
Markus Armbruster
3
-3
/
+0
2023-02-21
target/microblaze: Add gdbstub xml
Richard Henderson
3
-12
/
+42
2023-02-21
target/i386/gdbstub: Fix a bug about order of FPU stack in 'g' packets.
TaiseiIto
1
-1
/
+3
2023-02-16
target/arm: Move cpregs code out of cpu.h
Fabiano Rosas
2
-91
/
+98
2023-02-16
target/arm: Move PC alignment check
Fabiano Rosas
1
-9
/
+9
2023-02-16
target/arm: wrap call to aarch64_sve_change_el in tcg_enabled()
Claudio Fontana
1
-5
/
+7
2023-02-16
target/arm: wrap psci call with tcg_enabled
Claudio Fontana
1
-1
/
+2
2023-02-16
target/arm: rename handle_semihosting to tcg_handle_semihosting
Claudio Fontana
1
-2
/
+2
2023-02-16
target/arm: Declare CPU <-> NVIC helpers in 'hw/intc/armv7m_nvic.h'
Philippe Mathieu-Daudé
4
-124
/
+9
2023-02-16
target/arm: Store CPUARMState::nvic as NVICState*
Philippe Mathieu-Daudé
3
-23
/
+26
2023-02-16
target/arm: Restrict CPUARMState::nvic to sysemu
Philippe Mathieu-Daudé
1
-1
/
+1
2023-02-16
target/arm: Restrict CPUARMState::arm_boot_info to sysemu
Philippe Mathieu-Daudé
1
-1
/
+1
2023-02-16
target/arm: Restrict CPUARMState::gicv3state to sysemu
Philippe Mathieu-Daudé
1
-1
/
+2
2023-02-16
target/arm: Avoid resetting CPUARMState::eabi field
Philippe Mathieu-Daudé
1
-5
/
+4
2023-02-16
target/arm: Convert CPUARMState::eabi to boolean
Philippe Mathieu-Daudé
1
-1
/
+1
2023-02-16
target/arm: Constify ID_PFR1 on user emulation
Philippe Mathieu-Daudé
1
-2
/
+10
2023-02-16
target/arm: Reduce arm_v7m_mmu_idx_[all/for_secstate_and_priv]() scope
Philippe Mathieu-Daudé
2
-51
/
+37
2023-02-16
target/arm: Simplify arm_v7m_mmu_idx_for_secstate() for user emulation
Philippe Mathieu-Daudé
1
-3
/
+8
2023-02-16
target/i386: Fix 32-bit AD[CO]X insns in 64-bit mode
Richard Henderson
1
-0
/
+2
2023-02-11
target/i386: fix ADOX followed by ADCX
Paolo Bonzini
1
-9
/
+11
2023-02-11
target/i386: Fix C flag for BLSI, BLSMSK, BLSR
Richard Henderson
1
-0
/
+3
2023-02-11
target/i386: Fix BEXTR instruction
Richard Henderson
1
-11
/
+11
2023-02-08
Merge tag 'pull-tricore-20230208' of https://github.com/bkoppelmann/qemu into...
Peter Maydell
1
-19
/
+22
2023-02-08
target/tricore: Fix OPC1_16_SRO_LD_H translation
Anton Kochkov
1
-1
/
+1
2023-02-08
target/tricore: Fix OPC2_32_BO_LD_BU_PREINC
Bastian Koppelmann
1
-1
/
+1
2023-02-08
target/tricore: Fix OPC2_32_RRRR_DEXTR
Bastian Koppelmann
1
-3
/
+12
2023-02-08
target/tricore: Fix RRPW_DEXTR
Bastian Koppelmann
1
-9
/
+3
2023-02-08
target/tricore: Fix OPC2_32_RCRW_INSERT translation
Bastian Koppelmann
1
-2
/
+2
2023-02-08
target/tricore: Fix OPC2_32_RCRW_IMASK translation
Bastian Koppelmann
1
-3
/
+3
2023-02-08
Drop duplicate #include
Markus Armbruster
3
-4
/
+0
2023-02-08
riscv: Clean up includes
Markus Armbruster
1
-1
/
+0
2023-02-08
target/hexagon: Clean up includes
Markus Armbruster
2
-2
/
+0
2023-02-07
target/riscv: fix SBI getchar handler for KVM
Vladimir Isaev
1
-2
/
+3
2023-02-07
target/riscv: fix ctzw behavior
Vladimir Isaev
1
-0
/
+1
2023-02-07
target/riscv: fix for virtual instr exception
Deepak Gupta
1
-0
/
+1
2023-02-07
RISC-V: Adding XTheadFmv ISA extension
Christoph Müllner
5
-3
/
+55
2023-02-07
RISC-V: Add initial support for T-Head C906
Christoph Müllner
3
-0
/
+38
2023-02-07
RISC-V: Set minimum priv version for Zfh to 1.11
Christoph Müllner
1
-1
/
+1
2023-02-07
RISC-V: Adding T-Head FMemIdx extension
Christoph Müllner
5
-1
/
+123
2023-02-07
RISC-V: Adding T-Head MemIdx extension
Christoph Müllner
5
-1
/
+464
2023-02-07
RISC-V: Adding T-Head MemPair extension
Christoph Müllner
5
-1
/
+109
2023-02-07
RISC-V: Adding T-Head multiply-accumulate instructions
Christoph Müllner
5
-1
/
+96
2023-02-07
RISC-V: Adding XTheadCondMov ISA extension
Christoph Müllner
5
-1
/
+43
2023-02-07
RISC-V: Adding XTheadBs ISA extension
Christoph Müllner
5
-1
/
+23
2023-02-07
RISC-V: Adding XTheadBb ISA extension
Christoph Müllner
5
-2
/
+149
2023-02-07
RISC-V: Adding XTheadBa ISA extension
Christoph Müllner
5
-1
/
+66
2023-02-07
RISC-V: Adding XTheadSync ISA extension
Christoph Müllner
7
-1
/
+105
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