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| author | Bastian Koppelmann <kbastian@mail.uni-paderborn.de> | 2023-02-02 13:04:23 +0100 |
|---|---|---|
| committer | Bastian Koppelmann <kbastian@mail.uni-paderborn.de> | 2023-02-08 09:57:11 +0100 |
| commit | 65e57fdb25a0df8950f107041550aeb178af41ad (patch) | |
| tree | 952c5edfd0b964082398a3a09acc9c50fada90e7 /target | |
| parent | 969d09c3a6186c0a4bc8a41db0c1aba1c76081fc (diff) | |
| download | qemu-65e57fdb25a0df8950f107041550aeb178af41ad.zip qemu-65e57fdb25a0df8950f107041550aeb178af41ad.tar.gz qemu-65e57fdb25a0df8950f107041550aeb178af41ad.tar.bz2 | |
target/tricore: Fix OPC2_32_RCRW_IMASK translation
we were mixing up the "c" and "d" registers. We used "d" as a
destination register und "c" as the source. According to the TriCore ISA
manual 1.6 vol 2 it is the other way round.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/653
Message-Id: <20230202120432.1268-2-kbastian@mail.uni-paderborn.de>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Diffstat (limited to 'target')
| -rw-r--r-- | target/tricore/translate.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/target/tricore/translate.c b/target/tricore/translate.c index df9e46c..8de4e56 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -5794,11 +5794,11 @@ static void decode_rcrw_insert(DisasContext *ctx) switch (op2) { case OPC2_32_RCRW_IMASK: - tcg_gen_andi_tl(temp, cpu_gpr_d[r4], 0x1f); + tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f); tcg_gen_movi_tl(temp2, (1 << width) - 1); - tcg_gen_shl_tl(cpu_gpr_d[r3 + 1], temp2, temp); + tcg_gen_shl_tl(cpu_gpr_d[r4 + 1], temp2, temp); tcg_gen_movi_tl(temp2, const4); - tcg_gen_shl_tl(cpu_gpr_d[r3], temp2, temp); + tcg_gen_shl_tl(cpu_gpr_d[r4], temp2, temp); break; case OPC2_32_RCRW_INSERT: temp3 = tcg_temp_new(); |