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2017-02-07
target/arm: A32, T32: Create Instruction Syndromes for Data Aborts
Peter Maydell
3
-63
/
+149
2017-02-07
target/arm: Abstract out pbit/wbit tests in ARM ldr/str decode
Peter Maydell
1
-3
/
+6
2017-02-07
arm: Correctly handle watchpoints for BE32 CPUs
Julian Brown
3
-0
/
+30
2017-02-07
Fix Thumb-1 BE32 execution and disassembly.
Julian Brown
2
-1
/
+32
2017-02-07
target/arm: Add cfgend parameter for ARM CPU selection.
Julian Brown
2
-0
/
+20
2017-02-06
target/hppa: Fix gdb_write_register
Richard Henderson
1
-0
/
+1
2017-02-06
target/hppa: Tidy do_cbranch
Richard Henderson
1
-12
/
+5
2017-02-02
Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.9-20170202' into...
Peter Maydell
24
-476
/
+2421
2017-02-02
ppc/kvm: Handle the "family" CPU via alias instead of registering new types
Thomas Huth
1
-13
/
+23
2017-02-02
target/ppc/mmu_hash64: Fix incorrect shift value in amr calculation
Suraj Jitindar Singh
1
-1
/
+1
2017-02-02
target/ppc/mmu_hash64: Fix printing unsigned as signed int
Suraj Jitindar Singh
1
-2
/
+2
2017-02-02
tcg/POWER9: NOOP the cp_abort instruction
Suraj Jitindar Singh
1
-0
/
+5
2017-02-02
target/ppc/debug: Print LPCR register value if register exists
Suraj Jitindar Singh
1
-0
/
+3
2017-02-02
target-ppc: Add xststdc[sp, dp, qp] instructions
Nikunj A Dadhania
5
-8
/
+69
2017-02-02
target-ppc: Add xvtstdc[sp,dp] instructions
Nikunj A Dadhania
5
-2
/
+55
2017-02-01
arm: add trailing ; after MISMATCH_CHECK
Michael S. Tsirkin
1
-49
/
+49
2017-02-01
arm: better stub version for MISMATCH_CHECK
Michael S. Tsirkin
1
-1
/
+3
2017-01-31
target/ppc/cpu-models: Fix/remove bad CPU aliases
Thomas Huth
1
-20
/
+2
2017-01-31
target/ppc: Remove unused POWERPC_FAMILY(POWER)
Thomas Huth
1
-22
/
+0
2017-01-31
spapr: clock should count only if vm is running
Laurent Vivier
1
-0
/
+3
2017-01-31
target/ppc: Add pcr_supported to POWER9 cpu class definition
Suraj Jitindar Singh
2
-0
/
+3
2017-01-31
powerpc/cpu-models: rename ISAv3.00 logical PVR definition
Suraj Jitindar Singh
1
-1
/
+1
2017-01-31
target-ppc: Add xvcv[hpsp, sphp] instructions
Nikunj A Dadhania
4
-9
/
+24
2017-01-31
target-ppc: Add xsmulqp instruction
Bharata B Rao
4
-0
/
+38
2017-01-31
target-ppc: Add xsdivqp instruction
Bharata B Rao
4
-0
/
+39
2017-01-31
target-ppc: Add xscvsdqp and xscvudqp instructions
Bharata B Rao
4
-0
/
+31
2017-01-31
target-ppc: Use ppc_vsr_t.f128 in xscmp[o,u,exp]qp
Bharata B Rao
1
-12
/
+8
2017-01-31
ppc: Implement bcdutrunc. instruction
Jose Ricardo Ziviani
4
-1
/
+57
2017-01-31
ppc: Implement bcdtrunc. instruction
Jose Ricardo Ziviani
4
-2
/
+45
2017-01-31
target-ppc: Add xscvqps[d,w]z instructions
Bharata B Rao
4
-0
/
+46
2017-01-31
target-ppc: Add xvxsigdp instruction
Nikunj A Dadhania
2
-0
/
+41
2017-01-31
target-ppc: Add xvxsigsp instruction
Nikunj A Dadhania
4
-0
/
+24
2017-01-31
target-ppc: Add xvxexpdp instruction
Nikunj A Dadhania
2
-0
/
+18
2017-01-31
target-ppc: Add xvxexpsp instruction
Nikunj A Dadhania
2
-0
/
+18
2017-01-31
target-ppc: Add xviexpdp instruction
Nikunj A Dadhania
2
-0
/
+27
2017-01-31
target-ppc: Add xviexpsp instruction
Nikunj A Dadhania
2
-0
/
+28
2017-01-31
target-ppc: Add xsiexpqp instruction
Nikunj A Dadhania
2
-0
/
+23
2017-01-31
target-ppc: Add xsiexpdp instruction
Nikunj A Dadhania
2
-0
/
+21
2017-01-31
ppc: Implement bcdsr. instruction
Jose Ricardo Ziviani
4
-0
/
+52
2017-01-31
ppc: Implement bcdus. instruction
Jose Ricardo Ziviani
4
-1
/
+46
2017-01-31
ppc: Implement bcds. instruction
Jose Ricardo Ziviani
4
-1
/
+46
2017-01-31
target-ppc: xscvqpdp zero VSR
Nikunj A Dadhania
1
-1
/
+1
2017-01-31
ppc: Fix a warning in bcdcfz code and improve BCD_DIG_BYTE macro
Jose Ricardo Ziviani
1
-3
/
+3
2017-01-31
target-ppc: Add xscvqpdp instruction
Bharata B Rao
4
-0
/
+31
2017-01-31
target-ppc: Add xscvdpqp instruction
Bharata B Rao
4
-0
/
+48
2017-01-31
target-ppc: Add xsaddqp instructions
Bharata B Rao
5
-0
/
+41
2017-01-31
ppc: Add ppc_set_compat_all()
David Gibson
2
-0
/
+38
2017-01-31
target-ppc: Add xsxsigqp instructions
Nikunj A Dadhania
2
-0
/
+30
2017-01-31
target-ppc: Add xsxsigdp instruction
Nikunj A Dadhania
2
-0
/
+30
2017-01-31
target-ppc: Add xsxexpqp instruction
Nikunj A Dadhania
2
-0
/
+16
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