riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2023-08-24	target/loongarch: Add avail_LAM to check atomic instructions	Song Gao	2	-36/+37
2023-08-24	target/loongarch: Add avail_LSPW to check LSPW instructions	Song Gao	2	-0/+9
2023-08-24	target/loongarch: Add avail_FP/FP_SP/FP_DP to check fpu instructions	Song Gao	7	-86/+159
2023-08-24	target/loongarch: Add LoongArch32 cpu la132	Jiajie Chen	1	-0/+30
2023-08-24	target/loongarch: Add avail_64 to check la64-only instructions	Song Gao	10	-123/+152
2023-08-24	target/loongarch: Add a check parameter to the TRANS macro	Song Gao	14	-944/+946
2023-08-24	target/loongarch: Sign extend results in VA32 mode	Jiajie Chen	1	-0/+3
2023-08-24	target/loongarch: Truncate high 32 bits of address in VA32 mode	Jiajie Chen	2	-2/+20
2023-08-24	target/loongarch: Extract set_pc() helper	Jiajie Chen	4	-11/+16
2023-08-24	target/loongarch: Extract make_address_pc() helper	Jiajie Chen	3	-3/+8
2023-08-24	target/loongarch: Extract make_address_i() helper	Jiajie Chen	6	-57/+29
2023-08-24	target/loongarch: Extract make_address_x() helper	Jiajie Chen	4	-20/+22
2023-08-24	target/loongarch: Add LA64 & VA32 to DisasContext	Jiajie Chen	3	-0/+18
2023-08-24	target/loongarch: Support LoongArch32 VPPN	Jiajie Chen	2	-7/+22
2023-08-24	target/loongarch: Support LoongArch32 DMW	Jiajie Chen	2	-7/+26
2023-08-24	target/loongarch: Support LoongArch32 TLB entry	Jiajie Chen	2	-9/+17
2023-08-24	target/loongarch: Add GDB support for loongarch32 mode	Jiajie Chen	2	-7/+35
2023-08-24	target/loongarch: Add new object class for loongarch32 cpus	Jiajie Chen	2	-0/+12
2023-08-24	target/loongarch: Add function to check current arch	Jiajie Chen	1	-0/+10
2023-08-24	target/loongarch: Extract 64-bit specifics to loongarch64_cpu_class_init	Philippe Mathieu-Daudé	1	-8/+15
2023-08-24	target/loongarch: Introduce abstract TYPE_LOONGARCH64_CPU	Philippe Mathieu-Daudé	2	-3/+10
2023-08-24	target/loongarch: Fix loongarch_la464_initfn() misses setting LSPW	Song Gao	1	-0/+1
2023-08-24	target/loongarch: Remove duplicated disas_set_info assignment	Philippe Mathieu-Daudé	1	-1/+0
2023-08-24	target/loongarch: Log I/O write accesses to CSR registers	Philippe Mathieu-Daudé	1	-0/+2
2023-08-23	target/s390x: Fix the "ignored match" case in VSTRS	Ilya Leoshkevich	1	-37/+17
2023-08-23	target/s390x: Use a 16-bit immediate in VREP	Ilya Leoshkevich	1	-2/+2
2023-08-23	target/s390x: Fix VSTL with a large length	Ilya Leoshkevich	1	-1/+1
2023-08-23	target/s390x: Check reserved bits of VFMIN/VFMAX's M5	Ilya Leoshkevich	1	-1/+1
2023-08-23	s390x: Convert DPRINTF to trace events	Cédric Le Goater	2	-22/+18
2023-08-22	target/arm: Fix 64-bit SSRA	Richard Henderson	1	-1/+1
2023-08-22	target/arm: Fix SME ST1Q	Richard Henderson	1	-1/+1
2023-08-22	target/arm/helper: Implement CNTHCTL_EL2.CNT[VP]MASK	Jean-Philippe Brucker	4	-14/+68
2023-08-22	target/arm/helper: Check SCR_EL3.{NSE, NS} encoding for AT instructions	Jean-Philippe Brucker	1	-11/+27
2023-08-22	target/arm: Pass security space rather than flag for AT instructions	Jean-Philippe Brucker	3	-30/+27
2023-08-22	target/arm: Skip granule protection checks for AT instructions	Jean-Philippe Brucker	3	-18/+26
2023-08-22	target/arm/helper: Fix tlbmask and tlbbits for TLBI VAE2*	Jean-Philippe Brucker	1	-10/+40
2023-08-22	target/arm/ptw: Load stage-2 tables from realm physical space	Jean-Philippe Brucker	1	-8/+18
2023-08-22	target/arm: Adjust PAR_EL1.SH for Device and Normal-NC memory types	Peter Maydell	1	-1/+14
2023-08-22	target/arm/ptw: Report stage 2 fault level for stage 2 faults on stage 1 ptw	Peter Maydell	1	-3/+7
2023-08-22	target/arm/ptw: Check for block descriptors at invalid levels	Peter Maydell	1	-2/+23
2023-08-22	target/arm/ptw: Set attributes correctly for MMU disabled data accesses	Peter Maydell	1	-5/+7
2023-08-22	target/arm/ptw: Drop S1Translate::out_secure	Peter Maydell	1	-5/+2
2023-08-22	target/arm/ptw: Remove S1Translate::in_secure	Peter Maydell	1	-13/+0
2023-08-22	target/arm/ptw: Remove last uses of ptw->in_secure	Peter Maydell	1	-4/+7
2023-08-22	target/arm/ptw: Only fold in NSTable bit effects in Secure state	Peter Maydell	1	-2/+1
2023-08-22	target/arm: Pass an ARMSecuritySpace to arm_is_el2_enabled_secstate()	Peter Maydell	2	-6/+9
2023-08-22	target/arm/ptw: Pass an ARMSecuritySpace to arm_hcr_el2_eff_secstate()	Peter Maydell	3	-12/+13
2023-08-22	target/arm/ptw: Pass ARMSecurityState to regime_translation_disabled()	Peter Maydell	1	-7/+8
2023-08-22	target/arm/ptw: Pass ptw into get_phys_addr_pmsa*() and get_phys_addr_disabled()	Peter Maydell	1	-21/+36
2023-08-22	target/arm/ptw: Set s1ns bit in fault info more consistently	Peter Maydell	1	-4/+15