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authorPeter Maydell <peter.maydell@linaro.org>2023-08-22 17:31:09 +0100
committerPeter Maydell <peter.maydell@linaro.org>2023-08-22 17:31:09 +0100
commit3d9ca96221ba7212aacb27ec472f0be703e99a78 (patch)
treec9c66d8a18927d450b984ec12a6b7449a2c62ca3 /target
parentb02f5e06bcc87a52b9955d1425faadc9ddc9d38e (diff)
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target/arm/ptw: Set attributes correctly for MMU disabled data accesses
When the MMU is disabled, data accesses should be Device nGnRnE, Outer Shareable, Untagged. We handle the other cases from AArch64.S1DisabledOutput() correctly but missed this one. Device nGnRnE is memattr == 0, so the only part we were missing was that shareability should be set to 2 for both insn fetches and data accesses. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230807141514.19075-13-peter.maydell@linaro.org
Diffstat (limited to 'target')
-rw-r--r--target/arm/ptw.c12
1 files changed, 7 insertions, 5 deletions
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 312ccab..7f217a3 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -3108,11 +3108,13 @@ static bool get_phys_addr_disabled(CPUARMState *env,
}
}
}
- if (memattr == 0 && access_type == MMU_INST_FETCH) {
- if (regime_sctlr(env, mmu_idx) & SCTLR_I) {
- memattr = 0xee; /* Normal, WT, RA, NT */
- } else {
- memattr = 0x44; /* Normal, NC, No */
+ if (memattr == 0) {
+ if (access_type == MMU_INST_FETCH) {
+ if (regime_sctlr(env, mmu_idx) & SCTLR_I) {
+ memattr = 0xee; /* Normal, WT, RA, NT */
+ } else {
+ memattr = 0x44; /* Normal, NC, No */
+ }
}
shareability = 2; /* outer shareable */
}