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| author | Jiajie Chen <c@jia.je> | 2023-08-22 09:19:53 +0200 |
|---|---|---|
| committer | Song Gao <gaosong@loongson.cn> | 2023-08-24 11:17:58 +0800 |
| commit | bb8710cf0a637c4af189675f234639ce9e90a27d (patch) | |
| tree | eb23fd92ca59eaed45fabed9a1eb40276052a890 /target | |
| parent | c0c0461e3a06c8e854b8666a2610b1b619d0d1f8 (diff) | |
| download | qemu-bb8710cf0a637c4af189675f234639ce9e90a27d.zip qemu-bb8710cf0a637c4af189675f234639ce9e90a27d.tar.gz qemu-bb8710cf0a637c4af189675f234639ce9e90a27d.tar.bz2 | |
target/loongarch: Add LoongArch32 cpu la132
Add LoongArch32 cpu la132.
Due to lack of public documentation of la132, it is currently a
synthetic LoongArch32 cpu model. Details need to be added in the future.
Signed-off-by: Jiajie Chen <c@jia.je>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20230822032724.1353391-10-gaosong@loongson.cn>
Message-Id: <20230822071959.35620-4-philmd@linaro.org>
Diffstat (limited to 'target')
| -rw-r--r-- | target/loongarch/cpu.c | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 67eb6c3..d3c3e0d 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -440,6 +440,35 @@ static void loongarch_la464_initfn(Object *obj) env->CSR_ASID = FIELD_DP64(0, CSR_ASID, ASIDBITS, 0xa); } +static void loongarch_la132_initfn(Object *obj) +{ + LoongArchCPU *cpu = LOONGARCH_CPU(obj); + CPULoongArchState *env = &cpu->env; + + int i; + + for (i = 0; i < 21; i++) { + env->cpucfg[i] = 0x0; + } + + cpu->dtb_compatible = "loongarch,Loongson-1C103"; + env->cpucfg[0] = 0x148042; /* PRID */ + + uint32_t data = 0; + data = FIELD_DP32(data, CPUCFG1, ARCH, 1); /* LA32 */ + data = FIELD_DP32(data, CPUCFG1, PGMMU, 1); + data = FIELD_DP32(data, CPUCFG1, IOCSR, 1); + data = FIELD_DP32(data, CPUCFG1, PALEN, 0x1f); /* 32 bits */ + data = FIELD_DP32(data, CPUCFG1, VALEN, 0x1f); /* 32 bits */ + data = FIELD_DP32(data, CPUCFG1, UAL, 1); + data = FIELD_DP32(data, CPUCFG1, RI, 0); + data = FIELD_DP32(data, CPUCFG1, EP, 0); + data = FIELD_DP32(data, CPUCFG1, RPLV, 0); + data = FIELD_DP32(data, CPUCFG1, HP, 1); + data = FIELD_DP32(data, CPUCFG1, IOCSR_BRD, 1); + env->cpucfg[1] = data; +} + static void loongarch_cpu_list_entry(gpointer data, gpointer user_data) { const char *typename = object_class_get_name(OBJECT_CLASS(data)); @@ -787,6 +816,7 @@ static const TypeInfo loongarch_cpu_type_infos[] = { .class_init = loongarch64_cpu_class_init, }, DEFINE_LOONGARCH_CPU_TYPE(64, "la464", loongarch_la464_initfn), + DEFINE_LOONGARCH_CPU_TYPE(32, "la132", loongarch_la132_initfn), }; DEFINE_TYPES(loongarch_cpu_type_infos) |