index
:
riscv-gnu-toolchain/qemu.git
block
master
stable-0.10
stable-0.11
stable-0.12
stable-0.13
stable-0.14
stable-0.15
stable-1.0
stable-1.1
stable-1.2
stable-1.3
stable-1.4
stable-1.5
stable-1.6
stable-1.7
stable-2.0
stable-2.1
stable-2.10
stable-2.11
stable-2.12
stable-2.2
stable-2.3
stable-2.4
stable-2.5
stable-2.6
stable-2.7
stable-2.8
stable-2.9
stable-3.0
stable-3.1
stable-4.0
stable-4.1
stable-4.2
stable-5.0
stable-6.0
stable-6.1
stable-7.2
stable-8.0
stable-8.1
stable-8.2
stable-9.0
stable-9.1
stable-9.2
staging
staging-7.2
staging-8.0
staging-8.1
staging-8.2
staging-9.0
staging-9.1
staging-9.2
Unnamed repository; edit this file 'description' to name the repository.
root
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
target
Age
Commit message (
Expand
)
Author
Files
Lines
2021-05-01
Hexagon (target/hexagon) cleanup reg_field_info definition
Taylor Simpson
2
-4
/
+3
2021-05-01
Hexagon (target/hexagon) cleanup ternary operators in semantics
Taylor Simpson
1
-6
/
+6
2021-05-01
Hexagon (target/hexagon) use softfloat for float-to-int conversions
Taylor Simpson
6
-259
/
+136
2021-05-01
Hexagon (target/hexagon) replace float32_mul_pow2 with float32_scalbn
Taylor Simpson
1
-17
/
+11
2021-05-01
Hexagon (target/hexagon) use softfloat default NaN and tininess
Taylor Simpson
2
-47
/
+5
2021-05-01
Hexagon (target/hexagon) change type of softfloat_roundingmodes
Taylor Simpson
1
-1
/
+1
2021-05-01
Hexagon (target/hexagon) remove unused carry_from_add64 function
Taylor Simpson
3
-16
/
+0
2021-05-01
Hexagon (target/hexagon) change variables from int to bool when appropriate
Taylor Simpson
6
-59
/
+60
2021-05-01
Hexagon (target/hexagon) decide if pred has been written at TCG gen time
Taylor Simpson
4
-10
/
+25
2021-05-01
Hexagon (target/hexagon) properly generate TB end for DISAS_NORETURN
Taylor Simpson
2
-32
/
+33
2021-05-01
Hexagon (target/hexagon) use env_archcpu and env_cpu
Taylor Simpson
4
-9
/
+4
2021-05-01
Hexagon (target/hexagon) remove unnecessary inline directives
Taylor Simpson
5
-47
/
+46
2021-05-01
Hexagon (target/hexagon) cleanup gen_log_predicated_reg_write_pair
Taylor Simpson
1
-14
/
+13
2021-05-01
Hexagon (target/hexagon) TCG generation cleanup
Taylor Simpson
1
-5
/
+9
2021-05-01
target/hexagon: remove unnecessary semicolons
Taylor Simpson
1
-2
/
+2
2021-05-01
target/hexagon: fix typo in comment
Taylor Simpson
1
-1
/
+1
2021-05-01
target/hexagon: Change DECODE_MAPPED_REG operand name to OPNUM
Taylor Simpson
1
-2
/
+2
2021-05-01
target/hexagon: remove unnecessary checks in find_iclass_slots
Taylor Simpson
1
-4
/
+0
2021-05-01
target/hexagon: translation changes
Taylor Simpson
1
-17
/
+9
2021-04-30
target/arm: Enforce alignment for sve LD1R
Richard Henderson
1
-1
/
+1
2021-04-30
target/arm: Enforce alignment for aa64 vector LDn/STn (single)
Richard Henderson
1
-4
/
+5
2021-04-30
target/arm: Enforce alignment for aa64 vector LDn/STn (multiple)
Richard Henderson
1
-4
/
+11
2021-04-30
target/arm: Use MemOp for size + endian in aa64 vector ld/st
Richard Henderson
1
-10
/
+10
2021-04-30
target/arm: Enforce alignment for aa64 load-acq/store-rel
Richard Henderson
1
-9
/
+14
2021-04-30
target/arm: Use finalize_memop for aa64 fpr load/store
Richard Henderson
1
-16
/
+26
2021-04-30
target/arm: Use finalize_memop for aa64 gpr load/store
Richard Henderson
1
-45
/
+33
2021-04-30
target/arm: Enforce alignment for VLDn/VSTn (single)
Richard Henderson
1
-6
/
+42
2021-04-30
target/arm: Enforce alignment for VLDn/VSTn (multiple)
Richard Henderson
1
-5
/
+22
2021-04-30
target/arm: Enforce alignment for VLDn (all lanes)
Richard Henderson
3
-9
/
+44
2021-04-30
target/arm: Enforce alignment for VLDR/VSTR
Richard Henderson
1
-6
/
+6
2021-04-30
target/arm: Enforce alignment for VLDM/VSTM
Richard Henderson
1
-4
/
+4
2021-04-30
target/arm: Enforce alignment for SRS
Richard Henderson
1
-2
/
+2
2021-04-30
target/arm: Enforce alignment for RFE
Richard Henderson
1
-2
/
+2
2021-04-30
target/arm: Enforce alignment for LDM/STM
Richard Henderson
1
-2
/
+2
2021-04-30
target/arm: Enforce alignment for LDA/LDAH/STL/STLH
Richard Henderson
1
-2
/
+2
2021-04-30
target/arm: Enforce word alignment for LDRD/STRD
Richard Henderson
1
-8
/
+8
2021-04-30
target/arm: Adjust gen_aa32_{ld, st}_i64 for align+endianness
Richard Henderson
2
-35
/
+49
2021-04-30
target/arm: Fix SCTLR_B test for TCGv_i64 load/store
Richard Henderson
1
-2
/
+2
2021-04-30
target/arm: Merge gen_aa32_frob64 into gen_aa32_ld_i64
Richard Henderson
1
-20
/
+15
2021-04-30
target/arm: Adjust gen_aa32_{ld, st}_i32 for align+endianness
Richard Henderson
3
-52
/
+77
2021-04-30
target/arm: Add ALIGN_MEM to TBFLAG_ANY
Richard Henderson
5
-6
/
+25
2021-04-30
target/arm: Move TBFLAG_ANY bits to the bottom
Richard Henderson
1
-7
/
+7
2021-04-30
target/arm: Move TBFLAG_AM32 bits to the top
Richard Henderson
1
-21
/
+21
2021-04-30
target/arm: Move mode specific TB flags to tb->cs_base
Richard Henderson
3
-26
/
+35
2021-04-30
target/arm: Introduce CPUARMTBFlags
Richard Henderson
5
-37
/
+57
2021-04-30
target/arm: Add wrapper macros for accessing tbflags
Richard Henderson
5
-92
/
+101
2021-04-30
target/arm: Rename TBFLAG_ANY, PSTATE_SS
Richard Henderson
4
-5
/
+5
2021-04-30
target/arm: Rename TBFLAG_A32, SCTLR_B
Richard Henderson
3
-3
/
+3
2021-04-30
target/arm: Fix decode of align in VLDST_single
Richard Henderson
2
-4
/
+4
2021-04-30
target/arm: Remove log2_esize parameter to gen_mte_checkN
Richard Henderson
3
-11
/
+10
[prev]
[next]