riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2023-06-19	target/arm: Convert load/store tags insns to decodetree	Peter Maydell	2	-177/+190
2023-06-19	target/arm: Convert load/store single structure to decodetree	Peter Maydell	2	-108/+127
2023-06-19	target/arm: Convert load/store (multiple structures) to decodetree	Peter Maydell	2	-108/+128
2023-06-19	target/arm: Convert LDAPR/STLR (imm) to decodetree	Peter Maydell	2	-84/+54
2023-06-19	target/arm: Convert load (pointer auth) insns to decodetree	Peter Maydell	2	-67/+23
2023-06-19	target/arm: Convert atomic memory ops to decodetree	Peter Maydell	2	-98/+70
2023-06-19	target/arm: Convert LDR/STR reg+reg to decodetree	Peter Maydell	2	-87/+98
2023-06-19	target/arm: Convert LDR/STR with 12-bit immediate to decodetree	Peter Maydell	2	-88/+41
2023-06-19	target/arm: Convert ld/st reg+imm9 insns to decodetree	Peter Maydell	2	-118/+149
2023-06-19	target/arm: Convert load/store-pair to decodetree	Peter Maydell	2	-196/+249
2023-06-19	target/arm: Convert load reg (literal) group to decodetree	Peter Maydell	2	-54/+35
2023-06-19	target/arm: Convert LDXP, STXP, CASP, CAS to decodetree	Peter Maydell	2	-76/+50
2023-06-19	target/arm: Convert load/store exclusive and ordered to decodetree	Peter Maydell	2	-62/+103
2023-06-19	target/arm: Convert exception generation instructions to decodetree	Peter Maydell	2	-106/+76
2023-06-19	target/arm: Convert MSR (reg), MRS, SYS, SYSL to decodetree	Peter Maydell	2	-28/+14
2023-06-19	target/arm: Convert MSR (immediate) to decodetree	Peter Maydell	2	-115/+123
2023-06-19	target/arm: Convert CFINV, XAFLAG and AXFLAG to decodetree	Peter Maydell	2	-27/+32
2023-06-19	target/arm: Convert barrier insns to decodetree	Peter Maydell	2	-53/+46
2023-06-19	target/arm: Convert hint instruction space to decodetree	Peter Maydell	2	-123/+185
2023-06-19	target/arm: Consistently use finalize_memop_asimd() for ASIMD loads/stores	Peter Maydell	1	-4/+6
2023-06-19	target/arm: Pass memop to gen_mte_check1_mmuidx() in reg_imm9 decode	Peter Maydell	1	-1/+1
2023-06-19	target/arm: Return correct result for LDG when ATA=0	Peter Maydell	1	-1/+5
2023-06-19	target/arm: Fix return value from LDSMIN/LDSMAX 8/16 bit atomics	Peter Maydell	1	-2/+16
2023-06-16	Merge tag 'pull-loongarch-20230616' of https://gitlab.com/gaosong/qemu into s...	Richard Henderson	2	-2/+4
2023-06-16	target/loongarch: Fix CSR.DMW0-3.VSEG check	Jiajie Chen	1	-2/+2
2023-06-16	hw/intc: Set physical cpuid route for LoongArch ipi device	Tianrui Zhao	1	-0/+2
2023-06-15	target/arm: Allow users to set the number of VFP registers	Cédric Le Goater	2	-0/+34
2023-06-14	Merge tag 'pull-riscv-to-apply-20230614' of https://github.com/alistair23/qem...	Richard Henderson	17	-498/+698
2023-06-13	target/i386: Rename helper template headers as '.h.inc'	Philippe Mathieu-Daudé	6	-11/+11
2023-06-13	target/i386/helper: Shuffle do_cpu_init()	Philippe Mathieu-Daudé	1	-8/+4
2023-06-13	target/i386/helper: Remove do_cpu_sipi() stub for user-mode emulation	Philippe Mathieu-Daudé	2	-4/+2
2023-06-13	target/hppa/meson: Only build int_helper.o with system emulation	Philippe Mathieu-Daudé	2	-4/+1
2023-06-13	target/riscv: Smepmp: Return error when access permission not allowed in PMP	Himanshu Chauhan	1	-8/+2
2023-06-13	target/riscv/vector_helper.c: Remove the check for extra tail elements	Xiao Wang	1	-16/+6
2023-06-13	target/riscv/vector_helper.c: clean up reference of MTYPE	Xiao Wang	1	-5/+1
2023-06-13	target/riscv: Fix initialized value for cur_pmmask	Weiwei Li	1	-2/+2
2023-06-13	target/riscv: Remove pc_succ_insn from DisasContext	Weiwei Li	1	-6/+1
2023-06-13	target/riscv: Enable PC-relative translation	Weiwei Li	4	-20/+74
2023-06-13	target/riscv: Use true diff for gen_pc_plus_diff	Weiwei Li	3	-12/+9
2023-06-13	target/riscv: Change gen_set_pc_imm to gen_update_pc	Weiwei Li	6	-13/+13
2023-06-13	target/riscv: Change gen_goto_tb to work on displacements	Weiwei Li	2	-5/+7
2023-06-13	target/riscv: Introduce cur_insn_len into DisasContext	Weiwei Li	1	-1/+3
2023-06-13	target/riscv: Fix target address to update badaddr	Weiwei Li	3	-20/+28
2023-06-13	target/riscv: Pass RISCVCPUConfig as target_info to disassemble_info	Weiwei Li	1	-0/+1
2023-06-13	target/riscv: Split RISCVCPUConfig declarations from cpu.h into cpu_cfg.h	Weiwei Li	2	-113/+137
2023-06-13	target/riscv: smstateen knobs	Mayuresh Chitale	1	-1/+2
2023-06-13	target/riscv: Reuse tb->flags.FS	Mayuresh Chitale	2	-3/+10
2023-06-13	target/riscv: smstateen check for fcsr	Mayuresh Chitale	1	-0/+15
2023-06-13	target/riscv: Update cur_pmmask/base when xl changes	Weiwei Li	1	-1/+8
2023-06-13	target/riscv: Fix pointer mask transformation for vector address	Weiwei Li	1	-1/+1