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author | Weiwei Li <liweiwei@iscas.ac.cn> | 2023-05-24 09:59:33 +0800 |
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committer | Alistair Francis <alistair.francis@wdc.com> | 2023-06-13 17:22:15 +1000 |
commit | 30a0d77622d105908e7d45cf34c73f781263ede5 (patch) | |
tree | ec0a4aa9db70f6d0549836fb497bec2c3605f3f7 /target | |
parent | 7b945bdc0b10eda16dbeafe6a4dc1480176db38e (diff) | |
download | qemu-30a0d77622d105908e7d45cf34c73f781263ede5.zip qemu-30a0d77622d105908e7d45cf34c73f781263ede5.tar.gz qemu-30a0d77622d105908e7d45cf34c73f781263ede5.tar.bz2 |
target/riscv: Update cur_pmmask/base when xl changes
write_mstatus() can only change current xl when in debug mode.
And we need update cur_pmmask/base in this case.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-Id: <20230524015933.17349-3-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target')
-rw-r--r-- | target/riscv/csr.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/target/riscv/csr.c b/target/riscv/csr.c index cf7da4f..ad73691 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1324,8 +1324,15 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno, mstatus = set_field(mstatus, MSTATUS64_SXL, xl); } env->mstatus = mstatus; - env->xl = cpu_recompute_xl(env); + /* + * Except in debug mode, UXL/SXL can only be modified by higher + * privilege mode. So xl will not be changed in normal mode. + */ + if (env->debugger) { + env->xl = cpu_recompute_xl(env); + riscv_cpu_update_mask(env); + } return RISCV_EXCP_NONE; } |