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2023-09-19target/hppa: Wire up diag instruction to support BTLBHelge Deller3-3/+105
2023-09-15target/hppa: Extract diagnose immediate valueHelge Deller1-1/+1
2023-09-15target/hppa: Add BTLB support to hppa TLB functionsHelge Deller4-30/+65
2023-09-13target/hppa: Allow up to 16 BTLB entriesHelge Deller1-1/+7
2023-09-11Merge tag 'pull-riscv-to-apply-20230911' of https://github.com/alistair23/qem...Stefan Hajnoczi23-438/+2477
2023-09-11Merge tag 'pull-target-arm-20230908' of https://git.linaro.org/people/pmaydel...Stefan Hajnoczi16-124/+701
2023-09-11target/riscv: don't read CSR in riscv_csrrw_do64Nikita Shubin1-9/+15
2023-09-11target/riscv: Align the AIA model to v1.0 ratified specTommy Wu1-2/+5
2023-09-11target/riscv/pmp.c: respect mseccfg.RLB for pmpaddrX changesLeon Schuermann1-0/+4
2023-09-11target/riscv: Allocate itrigger timers only onceAkihiko Odaki3-5/+21
2023-09-11target/riscv: Use accelerated helper for AES64KS1IArd Biesheuvel1-12/+5
2023-09-11hw/intc/riscv_aplic.c fix non-KVM --enable-debug buildDaniel Henrique Barboza2-0/+6
2023-09-11riscv: zicond: make non-experimentalVineet Gupta1-1/+1
2023-09-11target/riscv: fix satp_mode_finalize() when satp_mode.supported = 0Daniel Henrique Barboza1-3/+20
2023-09-11target/riscv: Update CSR bits name for svadu extensionWeiwei Li4-15/+15
2023-09-11target/riscv: Create an KVM AIA irqchipYong-Xuan Wang2-0/+190
2023-09-11target/riscv: check the in-kernel irqchip supportYong-Xuan Wang1-1/+9
2023-09-11target/riscv: Fix zfa fleq.d and fltq.dLIU Zhiwei1-2/+2
2023-09-11target/riscv: Add Zihintntl extension ISA string to DTSJason Chien2-0/+3
2023-09-11target/riscv: Implement WARL behaviour for mcountinhibit/mcounterenRob Bradford1-2/+9
2023-09-11target/riscv: Add Zvksed ISA extension supportMax Chou6-1/+184
2023-09-11crypto: Create sm4_subwordMax Chou1-8/+2
2023-09-11target/riscv: Add Zvkg ISA extension supportNazar Kazakov6-2/+114
2023-09-11target/riscv: Add Zvksh ISA extension supportLawrence Hunter6-2/+177
2023-09-11target/riscv: Add Zvknh ISA extension supportKiran Ostrolenk6-3/+390
2023-09-11target/riscv: Add Zvkned ISA extension supportNazar Kazakov6-1/+381
2023-09-11target/riscv: Add Zvbb ISA extension supportDickon Hood6-0/+397
2023-09-11target/riscv: Refactor some of the generic vector functionalityKiran Ostrolenk2-42/+46
2023-09-11target/riscv: Refactor translation of vector-widening instructionDickon Hood1-29/+23
2023-09-11target/riscv: Move vector translation checksNazar Kazakov1-16/+12
2023-09-11target/riscv: Add Zvbc ISA extension supportLawrence Hunter8-1/+146
2023-09-11target/riscv: Remove redundant "cpu_vl == 0" checksNazar Kazakov1-30/+1
2023-09-11target/riscv: Refactor vector-vector translation macroKiran Ostrolenk1-30/+32
2023-09-11target/riscv: Refactor some of the generic vector functionalityKiran Ostrolenk4-200/+265
2023-09-11target/riscv: Use existing lookup tables for MixColumnsArd Biesheuvel1-30/+4
2023-09-11target/riscv: Fix page_check_range use in fault-only-firstLIU Zhiwei1-1/+1
2023-09-11target/riscv/cpu.c: add smepmp isa stringDaniel Henrique Barboza1-0/+1
2023-09-11target/riscv/cpu.c: add zmmul isa stringDaniel Henrique Barboza1-0/+1
2023-09-11target/riscv/cpu.c: do not run 'host' CPU with TCGDaniel Henrique Barboza1-0/+5
2023-09-08arm/kvm: Enable support for KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZEShameer Kolothum1-0/+61
2023-09-08target/arm: Enable SCTLR_EL1.TIDCP for user-onlyRichard Henderson1-0/+4
2023-09-08target/arm: Implement FEAT_TIDCP1Richard Henderson6-0/+38
2023-09-08target/arm: Implement HCR_EL2.TIDCPRichard Henderson4-2/+55
2023-09-08target/arm: Implement cortex-a710Richard Henderson1-0/+212
2023-09-08target/arm: Implement RMR_ELxRichard Henderson1-23/+41
2023-09-08arm64: Restore trapless ptimer accessColton Lewis1-0/+1
2023-09-08target/arm: Do not use gen_mte_checkN in trans_STGPRichard Henderson1-26/+15
2023-09-08target/arm: Implement FEAT_FPAC and FEAT_FPACCOMBINEAaron Lindsay3-2/+25
2023-09-08target/arm: Inform helpers whether a PAC instruction is 'combined'Aaron Lindsay3-19/+68
2023-09-08target/arm: Implement FEAT_Pauth2Aaron Lindsay2-5/+18
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