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author | Daniel Henrique Barboza <dbarboza@ventanamicro.com> | 2023-07-21 10:34:11 -0300 |
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committer | Alistair Francis <alistair.francis@wdc.com> | 2023-09-11 11:45:54 +1000 |
commit | 782ee711be9390f3586e615be49585aefd7fcaac (patch) | |
tree | 17221771b092687aee443d4d0c01e4676ccb1b51 /target | |
parent | c5ea91da443b458352c1b629b490ee6631775cb4 (diff) | |
download | qemu-782ee711be9390f3586e615be49585aefd7fcaac.zip qemu-782ee711be9390f3586e615be49585aefd7fcaac.tar.gz qemu-782ee711be9390f3586e615be49585aefd7fcaac.tar.bz2 |
target/riscv/cpu.c: do not run 'host' CPU with TCG
The 'host' CPU is available in a CONFIG_KVM build and it's currently
available for all accels, but is a KVM only CPU. This means that in a
RISC-V KVM capable host we can do things like this:
$ ./build/qemu-system-riscv64 -M virt,accel=tcg -cpu host --nographic
qemu-system-riscv64: H extension requires priv spec 1.12.0
This CPU does not have a priv spec because we don't filter its extensions
via priv spec. We shouldn't be reaching riscv_cpu_realize_tcg() at all
with the 'host' CPU.
We don't have a way to filter the 'host' CPU out of the available CPU
options (-cpu help) if the build includes both KVM and TCG. What we can
do is to error out during riscv_cpu_realize_tcg() if the user chooses
the 'host' CPU with accel=tcg:
$ ./build/qemu-system-riscv64 -M virt,accel=tcg -cpu host --nographic
qemu-system-riscv64: 'host' CPU is not compatible with TCG acceleration
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230721133411.474105-1-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target')
-rw-r--r-- | target/riscv/cpu.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6b93b04..08db3d6 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1395,6 +1395,11 @@ static void riscv_cpu_realize_tcg(DeviceState *dev, Error **errp) CPURISCVState *env = &cpu->env; Error *local_err = NULL; + if (object_dynamic_cast(OBJECT(dev), TYPE_RISCV_CPU_HOST)) { + error_setg(errp, "'host' CPU is not compatible with TCG acceleration"); + return; + } + riscv_cpu_validate_misa_mxl(cpu, &local_err); if (local_err != NULL) { error_propagate(errp, local_err); |