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author | Akihiko Odaki <akihiko.odaki@daynix.com> | 2024-02-03 19:11:10 +0900 |
---|---|---|
committer | Alistair Francis <alistair.francis@wdc.com> | 2024-02-09 20:43:14 +1000 |
commit | 1563cdb439e93a37c9bf8570ed80abc3a429d71b (patch) | |
tree | 434068aaa91ae21d4749538e62075cbc749f17b9 /target | |
parent | 742cc269c7e67352ebeecc528b0ade547a24de72 (diff) | |
download | qemu-1563cdb439e93a37c9bf8570ed80abc3a429d71b.zip qemu-1563cdb439e93a37c9bf8570ed80abc3a429d71b.tar.gz qemu-1563cdb439e93a37c9bf8570ed80abc3a429d71b.tar.bz2 |
target/riscv: Validate misa_mxl_max only once
misa_mxl_max is now a class member and initialized only once for each
class. This also moves the initialization of gdb_core_xml_file which
will be referenced before realization in the future.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240203-riscv-v11-3-a23f4848a628@daynix.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target')
-rw-r--r-- | target/riscv/cpu.c | 21 | ||||
-rw-r--r-- | target/riscv/tcg/tcg-cpu.c | 23 |
2 files changed, 21 insertions, 23 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0e6762b..be3ec5a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1349,6 +1349,26 @@ static const MISAExtInfo misa_ext_info_arr[] = { MISA_EXT_INFO(RVB, "x-b", "Bit manipulation (Zba_Zbb_Zbs)") }; +static void riscv_cpu_validate_misa_mxl(RISCVCPUClass *mcc) +{ + CPUClass *cc = CPU_CLASS(mcc); + + /* Validate that MISA_MXL is set properly. */ + switch (mcc->misa_mxl_max) { +#ifdef TARGET_RISCV64 + case MXL_RV64: + case MXL_RV128: + cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; + break; +#endif + case MXL_RV32: + cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; + break; + default: + g_assert_not_reached(); + } +} + static int riscv_validate_misa_info_idx(uint32_t bit) { int idx; @@ -2309,6 +2329,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); mcc->misa_mxl_max = (uint32_t)(uintptr_t)data; + riscv_cpu_validate_misa_mxl(mcc); } static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index d7639d8..dd5228c 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -268,27 +268,6 @@ static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) } } -static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu) -{ - RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); - CPUClass *cc = CPU_CLASS(mcc); - - /* Validate that MISA_MXL is set properly. */ - switch (mcc->misa_mxl_max) { -#ifdef TARGET_RISCV64 - case MXL_RV64: - case MXL_RV128: - cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; - break; -#endif - case MXL_RV32: - cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; - break; - default: - g_assert_not_reached(); - } -} - static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, Error **errp) { @@ -911,8 +890,6 @@ static bool riscv_tcg_cpu_realize(CPUState *cs, Error **errp) return false; } - riscv_cpu_validate_misa_mxl(cpu); - #ifndef CONFIG_USER_ONLY CPURISCVState *env = &cpu->env; Error *local_err = NULL; |