aboutsummaryrefslogtreecommitdiff
path: root/target
AgeCommit message (Expand)AuthorFilesLines
2021-10-29Merge remote-tracking branch 'remotes/ehabkost/tags/x86-next-pull-request' in...Richard Henderson1-1/+2
2021-10-29target/i386: Remove core-capability in Snowridge CPU modelChenyi Qiang1-1/+2
2021-10-29Merge remote-tracking branch 'remotes/alistair23/tags/pull-riscv-to-apply-202...Richard Henderson12-57/+527
2021-10-29Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20211028' into stagingRichard Henderson1-9/+14
2021-10-29target/riscv: change the api for RVF/RVD fmin/fmaxChih-Min Chao1-4/+12
2021-10-29target/riscv: remove force HS exceptionJose Martins3-33/+1
2021-10-29target/riscv: fix VS interrupts forwarding to HSJose Martins1-20/+8
2021-10-28Hexagon (target/hexagon) put writes to USR into temp until commitTaylor Simpson4-2/+12
2021-10-28Hexagon (target/hexagon) more tcg_constant_*Taylor Simpson4-21/+9
2021-10-28target/riscv: Allow experimental J-ext to be turned onAlexey Baturo1-0/+4
2021-10-28target/riscv: Implement address masking functions required for RISC-V Pointer...Anatoly Parshintsev3-2/+57
2021-10-28target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instr...Alexey Baturo5-0/+17
2021-10-28target/riscv: Print new PM CSRs in QEMU logsAlexey Baturo1-0/+7
2021-10-28target/riscv: Add J extension state descriptionAlexey Baturo1-0/+27
2021-10-28target/riscv: Support CSRs required for RISC-V PM extension except for the h-...Alexey Baturo3-0/+298
2021-10-28target/riscv: Add CSR defines for RISC-V PM extensionAlexey Baturo1-0/+96
2021-10-28target/riscv: Add J-extension into RISC-VAlexey Baturo1-0/+2
2021-10-27host-utils: add 128-bit quotient support to divu128/divs128Luis Pires1-4/+5
2021-10-27host-utils: move checks out of divu128/divs128Luis Pires1-5/+9
2021-10-23Merge remote-tracking branch 'remotes/vivier/tags/trivial-branch-for-6.2-pull...Richard Henderson1-5/+1
2021-10-22disas/nios2: Simplify endianess conversionPhilippe Mathieu-Daudé1-5/+1
2021-10-22target/riscv: Compute mstatus.sd on demandRichard Henderson3-20/+25
2021-10-22target/riscv: Use riscv_csrrw_debug for cpu_dumpRichard Henderson1-44/+45
2021-10-22target/riscv: Use gen_shift*_per_ol for RVB, RVIRichard Henderson3-52/+97
2021-10-22target/riscv: Use gen_unary_per_ol for RVBRichard Henderson2-17/+32
2021-10-22target/riscv: Adjust trans_rev8_32 for riscv64Richard Henderson1-1/+6
2021-10-22target/riscv: Use gen_arith_per_ol for RVMRichard Henderson2-3/+39
2021-10-22target/riscv: Replace DisasContext.w with DisasContext.olRichard Henderson4-43/+62
2021-10-22target/riscv: Replace is_32bit with get_xl/get_xlenRichard Henderson1-14/+17
2021-10-22target/riscv: Properly check SEW in amo_opRichard Henderson1-12/+14
2021-10-22target/riscv: Use REQUIRE_64BIT in amo_check64Richard Henderson1-1/+2
2021-10-22target/riscv: Add MXL/SXL/UXL to TB_FLAGSRichard Henderson5-1/+47
2021-10-22target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxlRichard Henderson6-32/+43
2021-10-22target/riscv: Split misa.mxl and misa.extRichard Henderson6-67/+98
2021-10-22target/riscv: Create RISCVMXL enumerationRichard Henderson1-3/+5
2021-10-22target/riscv: Move cpu_get_tb_cpu_state out of lineRichard Henderson2-45/+48
2021-10-22target/riscv: Organise the CPU propertiesAlistair Francis1-7/+10
2021-10-22target/riscv: Remove some unused macrosAlistair Francis1-8/+0
2021-10-22target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvhFrank Chang2-8/+8
2021-10-22target/riscv: Fix orc.b implementationPhilipp Tomsich1-5/+8
2021-10-22target/riscv: line up all of the registers in the info register dumpTravis Geiselbrecht1-5/+5
2021-10-22target/riscv: Pass the same value to oprsz and maxsz for vmv.v.vFrank Chang1-1/+2
2021-10-21target/ppc: adding user read/write functions for PMCsDaniel Henrique Barboza3-6/+80
2021-10-21target/ppc: add user read/write functions for MMCR2Daniel Henrique Barboza4-12/+99
2021-10-21target/ppc: add user read/write functions for MMCR0Gustavo Romero5-1/+128
2021-10-21target/ppc: add MMCR0 PMCC bits to hflagsDaniel Henrique Barboza3-0/+16
2021-10-21target/ppc: Filter mtmsr[d] input before setting MSRMatheus Ferst2-33/+41
2021-10-21target/ppc: Fix XER access in monitorMatheus Ferst1-1/+8
2021-10-21linux-user: Fix XER access in ppc version of elf_core_copy_regsMatheus Ferst2-2/+2
2021-10-21target/ppc: Fix XER access in gdbstubMatheus Ferst1-4/+4