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2017-02-07target/arm: A32, T32: Create Instruction Syndromes for Data AbortsPeter Maydell3-63/+149
2017-02-07target/arm: Abstract out pbit/wbit tests in ARM ldr/str decodePeter Maydell1-3/+6
2017-02-07arm: Correctly handle watchpoints for BE32 CPUsJulian Brown3-0/+30
2017-02-07Fix Thumb-1 BE32 execution and disassembly.Julian Brown2-1/+32
2017-02-07target/arm: Add cfgend parameter for ARM CPU selection.Julian Brown2-0/+20
2017-02-06target/hppa: Fix gdb_write_registerRichard Henderson1-0/+1
2017-02-06target/hppa: Tidy do_cbranchRichard Henderson1-12/+5
2017-02-02Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.9-20170202' into...Peter Maydell24-476/+2421
2017-02-02ppc/kvm: Handle the "family" CPU via alias instead of registering new typesThomas Huth1-13/+23
2017-02-02target/ppc/mmu_hash64: Fix incorrect shift value in amr calculationSuraj Jitindar Singh1-1/+1
2017-02-02target/ppc/mmu_hash64: Fix printing unsigned as signed intSuraj Jitindar Singh1-2/+2
2017-02-02tcg/POWER9: NOOP the cp_abort instructionSuraj Jitindar Singh1-0/+5
2017-02-02target/ppc/debug: Print LPCR register value if register existsSuraj Jitindar Singh1-0/+3
2017-02-02target-ppc: Add xststdc[sp, dp, qp] instructionsNikunj A Dadhania5-8/+69
2017-02-02target-ppc: Add xvtstdc[sp,dp] instructionsNikunj A Dadhania5-2/+55
2017-02-01arm: add trailing ; after MISMATCH_CHECKMichael S. Tsirkin1-49/+49
2017-02-01arm: better stub version for MISMATCH_CHECKMichael S. Tsirkin1-1/+3
2017-01-31target/ppc/cpu-models: Fix/remove bad CPU aliasesThomas Huth1-20/+2
2017-01-31target/ppc: Remove unused POWERPC_FAMILY(POWER)Thomas Huth1-22/+0
2017-01-31spapr: clock should count only if vm is runningLaurent Vivier1-0/+3
2017-01-31target/ppc: Add pcr_supported to POWER9 cpu class definitionSuraj Jitindar Singh2-0/+3
2017-01-31powerpc/cpu-models: rename ISAv3.00 logical PVR definitionSuraj Jitindar Singh1-1/+1
2017-01-31target-ppc: Add xvcv[hpsp, sphp] instructionsNikunj A Dadhania4-9/+24
2017-01-31target-ppc: Add xsmulqp instructionBharata B Rao4-0/+38
2017-01-31target-ppc: Add xsdivqp instructionBharata B Rao4-0/+39
2017-01-31target-ppc: Add xscvsdqp and xscvudqp instructionsBharata B Rao4-0/+31
2017-01-31target-ppc: Use ppc_vsr_t.f128 in xscmp[o,u,exp]qpBharata B Rao1-12/+8
2017-01-31ppc: Implement bcdutrunc. instructionJose Ricardo Ziviani4-1/+57
2017-01-31ppc: Implement bcdtrunc. instructionJose Ricardo Ziviani4-2/+45
2017-01-31target-ppc: Add xscvqps[d,w]z instructionsBharata B Rao4-0/+46
2017-01-31target-ppc: Add xvxsigdp instructionNikunj A Dadhania2-0/+41
2017-01-31target-ppc: Add xvxsigsp instructionNikunj A Dadhania4-0/+24
2017-01-31target-ppc: Add xvxexpdp instructionNikunj A Dadhania2-0/+18
2017-01-31target-ppc: Add xvxexpsp instructionNikunj A Dadhania2-0/+18
2017-01-31target-ppc: Add xviexpdp instructionNikunj A Dadhania2-0/+27
2017-01-31target-ppc: Add xviexpsp instructionNikunj A Dadhania2-0/+28
2017-01-31target-ppc: Add xsiexpqp instructionNikunj A Dadhania2-0/+23
2017-01-31target-ppc: Add xsiexpdp instructionNikunj A Dadhania2-0/+21
2017-01-31ppc: Implement bcdsr. instructionJose Ricardo Ziviani4-0/+52
2017-01-31ppc: Implement bcdus. instructionJose Ricardo Ziviani4-1/+46
2017-01-31ppc: Implement bcds. instructionJose Ricardo Ziviani4-1/+46
2017-01-31target-ppc: xscvqpdp zero VSRNikunj A Dadhania1-1/+1
2017-01-31ppc: Fix a warning in bcdcfz code and improve BCD_DIG_BYTE macroJose Ricardo Ziviani1-3/+3
2017-01-31target-ppc: Add xscvqpdp instructionBharata B Rao4-0/+31
2017-01-31target-ppc: Add xscvdpqp instructionBharata B Rao4-0/+48
2017-01-31target-ppc: Add xsaddqp instructionsBharata B Rao5-0/+41
2017-01-31ppc: Add ppc_set_compat_all()David Gibson2-0/+38
2017-01-31target-ppc: Add xsxsigqp instructionsNikunj A Dadhania2-0/+30
2017-01-31target-ppc: Add xsxsigdp instructionNikunj A Dadhania2-0/+30
2017-01-31target-ppc: Add xsxexpqp instructionNikunj A Dadhania2-0/+16
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