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2024-02-14target/i386/cpu: Fix typo in commentBernhard Beschow1-1/+1
2024-02-14apic, i386/tcg: add x2apic transitionsBui Quang Minh4-7/+23
2024-02-14apic: add support for x2APIC modeBui Quang Minh2-1/+19
2024-02-14i386/tcg: implement x2APIC registers MSR accessBui Quang Minh2-0/+30
2024-02-09target/riscv: add rv32i, rv32e and rv64e CPUsDaniel Henrique Barboza2-0/+24
2024-02-09target/riscv/cpu.c: add riscv_bare_cpu_init()Daniel Henrique Barboza1-16/+29
2024-02-09target/riscv: Enable xtheadsync under user modeLIU Zhiwei1-10/+0
2024-02-09target/riscv: support new isa extension detection devicetree propertiesConor Dooley2-0/+55
2024-02-09target/riscv: use misa_mxl_max to populate isa string rather than TARGET_LONG...Conor Dooley3-2/+11
2024-02-09target/riscv: Expose Zaamo and Zalrsc extensionsRob Bradford1-0/+5
2024-02-09target/riscv: Check 'A' and split extensions for atomic instructionsRob Bradford1-22/+34
2024-02-09target/riscv: Add Zaamo and Zalrsc extension infrastructureRob Bradford1-0/+2
2024-02-09target/riscv: Use RISCVException as return type for all csr opsLIU Zhiwei1-43/+74
2024-02-09target/riscv: FCSR doesn't contain vxrm and vxsatLIU Zhiwei1-8/+0
2024-02-09target/riscv: Validate misa_mxl_max only onceAkihiko Odaki2-23/+21
2024-02-09target/riscv: Move misa_mxl_max to classAkihiko Odaki7-98/+110
2024-02-09target/riscv: Remove misa_mxl validationAkihiko Odaki1-12/+3
2024-02-09target/riscv/kvm: get/set vector vregs[]Daniel Henrique Barboza1-2/+55
2024-02-09target/riscv/kvm: initialize 'vlenb' via get-reg-listDaniel Henrique Barboza1-3/+82
2024-02-09target/riscv/kvm: change kvm_reg_id to uint64_tDaniel Henrique Barboza1-1/+1
2024-02-09target/riscv/cpu.c: remove cpu->cfg.vlenDaniel Henrique Barboza3-7/+6
2024-02-09trans_rvv.c.inc: use vext_get_vlmax() in trans_vrgather_v*()Daniel Henrique Barboza1-4/+2
2024-02-09target/riscv: change vext_get_vlmax() argumentsDaniel Henrique Barboza3-14/+20
2024-02-09target/riscv/cpu.h: use 'vlenb' in vext_get_vlmax()Daniel Henrique Barboza1-2/+9
2024-02-09target/riscv/insn_trans/trans_rvv.c.inc: use 'vlenb' in MAXSZ()Daniel Henrique Barboza1-3/+3
2024-02-09target/riscv/vector_helper.c: use vlenb in HELPER(vsetvl)Daniel Henrique Barboza1-2/+9
2024-02-09target/riscv/vector_helper.c: use 'vlenb'Daniel Henrique Barboza1-9/+9
2024-02-09target/riscv/insn_trans/trans_rvvk.c.inc: use 'vlenb'Daniel Henrique Barboza1-8/+8
2024-02-09target/riscv/insn_trans/trans_rvv.c.inc: use 'vlenb'Daniel Henrique Barboza1-70/+70
2024-02-09target/riscv/insn_trans/trans_rvbf16.c.inc: use cpu->cfg.vlenbDaniel Henrique Barboza1-6/+6
2024-02-09target/riscv/gdbstub.c: use 'vlenb' instead of shifting 'vlen'Daniel Henrique Barboza1-3/+3
2024-02-09target/riscv/csr.c: use 'vlenb' instead of 'vlen'Daniel Henrique Barboza1-2/+2
2024-02-09target/riscv: add 'vlenb' field in cpu->cfgDaniel Henrique Barboza2-1/+4
2024-02-09target/riscv: Implement optional CSR mcontext of debug Sdtrig extensionAlvin Chang4-5/+41
2024-02-09target/riscv/cpu.c: move 'marchid' to riscv_cpu_properties[]Daniel Henrique Barboza1-53/+57
2024-02-09target/riscv/cpu.c: move 'mimpid' to riscv_cpu_properties[]Daniel Henrique Barboza1-32/+36
2024-02-09target/riscv/cpu.c: move 'mvendorid' to riscv_cpu_properties[]Daniel Henrique Barboza1-32/+37
2024-02-09target/riscv: remove riscv_cpu_options[]Daniel Henrique Barboza4-19/+0
2024-02-09target/riscv: move 'cboz_blocksize' to riscv_cpu_properties[]Daniel Henrique Barboza2-29/+37
2024-02-09target/riscv: move 'cbop_blocksize' to riscv_cpu_properties[]Daniel Henrique Barboza1-1/+37
2024-02-09target/riscv: move 'cbom_blocksize' to riscv_cpu_properties[]Daniel Henrique Barboza2-5/+38
2024-02-09target/riscv: create finalize_features() for KVMDaniel Henrique Barboza4-5/+72
2024-02-09target/riscv: move 'elen' to riscv_cpu_properties[]Daniel Henrique Barboza2-7/+42
2024-02-09target/riscv: move 'vlen' to riscv_cpu_properties[]Daniel Henrique Barboza2-6/+44
2024-02-09target/riscv: rework 'vext_spec'Daniel Henrique Barboza4-18/+34
2024-02-09target/riscv: rework 'priv_spec'Daniel Henrique Barboza4-31/+75
2024-02-09target/riscv: move 'pmp' to riscv_cpu_properties[]Daniel Henrique Barboza1-2/+36
2024-02-09target/riscv: move 'mmu' to riscv_cpu_properties[]Daniel Henrique Barboza1-4/+51
2024-02-09target/riscv: move 'pmu-mask' and 'pmu-num' to riscv_cpu_properties[]Daniel Henrique Barboza1-7/+84
2024-02-09target/riscv: make riscv_cpu_is_vendor() publicDaniel Henrique Barboza3-5/+6
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