| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2024-05-26 | target/i386: Add {hw,sw}_reserved to X86LegacyXSaveArea | Richard Henderson | 1 | -14/+25 |
| 2024-05-26 | target/i386: Add rbfm argument to cpu_x86_{xsave,xrstor} | Richard Henderson | 2 | -6/+6 |
| 2024-05-26 | target/i386: Split out do_xsave_chk | Richard Henderson | 1 | -24/+27 |
| 2024-05-26 | target/i386: Convert do_xrstor_* to X86Access | Richard Henderson | 1 | -20/+31 |
| 2024-05-26 | target/i386: Convert do_xsave_* to X86Access | Richard Henderson | 1 | -21/+26 |
| 2024-05-26 | tagret/i386: Convert do_fxsave, do_fxrstor to X86Access | Richard Henderson | 1 | -30/+42 |
| 2024-05-26 | target/i386: Convert do_xrstor_{fpu,mxcr,sse} to X86Access | Richard Henderson | 1 | -18/+28 |
| 2024-05-26 | target/i386: Convert do_xsave_{fpu,mxcr,sse} to X86Access | Richard Henderson | 1 | -21/+31 |
| 2024-05-26 | target/i386: Convert do_fsave, do_frstor to X86Access | Richard Henderson | 1 | -27/+33 |
| 2024-05-26 | target/i386: Convert do_fstenv to X86Access | Richard Henderson | 1 | -21/+24 |
| 2024-05-26 | target/i386: Convert do_fldenv to X86Access | Richard Henderson | 1 | -16/+14 |
| 2024-05-26 | target/i386: Convert helper_{fbld,fbst}_ST0 to X86Access | Richard Henderson | 1 | -10/+15 |
| 2024-05-26 | target/i386: Convert do_fldt, do_fstt to X86Access | Richard Henderson | 1 | -13/+31 |
| 2024-05-26 | target/i386: Add tcg/access.[ch] | Richard Henderson | 3 | -0/+210 |
| 2024-05-23 | Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging | Richard Henderson | 9 | -102/+321 |
| 2024-05-23 | target/loongarch: Add loongarch vector property unconditionally | Bibo Mao | 1 | -10/+4 |
| 2024-05-23 | target/loongarch/kvm: fpu save the vreg registers high 192bit | Song Gao | 1 | -0/+6 |
| 2024-05-23 | target/loongarch/kvm: Fix VM recovery from disk failures | Song Gao | 1 | -2/+4 |
| 2024-05-22 | target-i386: hyper-v: Correct kvm_hv_handle_exit return value | donsheng | 1 | -1/+1 |
| 2024-05-22 | i386/cpu: Use CPUCacheInfo.share_level to encode CPUID[0x8000001D].EAX[bits 2... | Zhao Liu | 1 | -9/+1 |
| 2024-05-22 | i386/cpu: Use CPUCacheInfo.share_level to encode CPUID[4] | Zhao Liu | 2 | -43/+56 |
| 2024-05-22 | i386: Add cache topology info in CPUCacheInfo | Zhao Liu | 2 | -0/+43 |
| 2024-05-22 | i386/cpu: Introduce module-id to X86CPU | Zhao Liu | 2 | -0/+3 |
| 2024-05-22 | i386: Expose module level in CPUID[0x1F] | Zhao Liu | 2 | -0/+7 |
| 2024-05-22 | i386: Support modules_per_die in X86CPUTopoInfo | Zhao Liu | 1 | -5/+8 |
| 2024-05-22 | i386: Introduce module level cpu topology to CPUX86State | Zhao Liu | 2 | -0/+4 |
| 2024-05-22 | i386/cpu: Decouple CPUID[0x1F] subleaf with specific topology level | Zhao Liu | 1 | -25/+110 |
| 2024-05-22 | i386: Split topology types of CPUID[0x1F] from the definitions of CPUID[0xB] | Zhao Liu | 2 | -11/+16 |
| 2024-05-22 | i386/cpu: Introduce bitmap to cache available CPU topology levels | Zhao Liu | 3 | -4/+21 |
| 2024-05-22 | i386/cpu: Consolidate the use of topo_info in cpu_x86_cpuid() | Zhao Liu | 1 | -13/+18 |
| 2024-05-22 | i386/cpu: Use APIC ID info get NumSharingCache for CPUID[0x8000001D].EAX[bits... | Zhao Liu | 1 | -4/+4 |
| 2024-05-22 | i386/cpu: Use APIC ID info to encode cache topo in CPUID[4] | Zhao Liu | 1 | -10/+40 |
| 2024-05-22 | i386/cpu: Fix i/d-cache topology to core level for Intel CPU | Zhao Liu | 1 | -2/+4 |
| 2024-05-22 | target/i386: add control bits support for LAM | Binbin Wu | 2 | -1/+10 |
| 2024-05-22 | target/i386: add support for LAM in CPUID enumeration | Robert Hoo | 2 | -1/+3 |
| 2024-05-22 | target/i386: clean up AAM/AAD | Paolo Bonzini | 4 | -19/+16 |
| 2024-05-22 | target/i386: generate simpler code for ROL/ROR with immediate count | Paolo Bonzini | 1 | -12/+14 |
| 2024-05-15 | Merge tag 'pull-hppa-20240515' of https://gitlab.com/rth7680/qemu into staging | Richard Henderson | 11 | -728/+842 |
| 2024-05-15 | target/hppa: Log cpu state on return-from-interrupt | Richard Henderson | 1 | -0/+12 |
| 2024-05-15 | target/hppa: Log cpu state at interrupt | Richard Henderson | 1 | -13/+14 |
| 2024-05-15 | target/hppa: Implement CF_PCREL | Richard Henderson | 2 | -32/+55 |
| 2024-05-15 | target/hppa: Adjust priv for B,GATE at runtime | Richard Henderson | 4 | -25/+47 |
| 2024-05-15 | target/hppa: Drop tlb_entry return from hppa_get_physical_address | Richard Henderson | 4 | -20/+7 |
| 2024-05-15 | target/hppa: Implement PSW_X | Richard Henderson | 1 | -17/+25 |
| 2024-05-15 | target/hppa: Implement PSW_B | Richard Henderson | 1 | -19/+6 |
| 2024-05-15 | target/hppa: Manage PSW_X and PSW_B in translator | Richard Henderson | 2 | -3/+57 |
| 2024-05-15 | target/hppa: Split PSW X and B into their own field | Richard Henderson | 2 | -4/+5 |
| 2024-05-15 | target/hppa: Improve hppa_cpu_dump_state | Richard Henderson | 1 | -6/+54 |
| 2024-05-15 | target/hppa: Do not mask in copy_iaoq_entry | Richard Henderson | 1 | -6/+1 |
| 2024-05-15 | target/hppa: Store full iaoq_f and page offset of iaoq_b in TB | Richard Henderson | 3 | -55/+48 |
