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AgeCommit message (Expand)AuthorFilesLines
2017-01-31target/ppc: Remove unused POWERPC_FAMILY(POWER)Thomas Huth1-22/+0
2017-01-31spapr: clock should count only if vm is runningLaurent Vivier1-0/+3
2017-01-31target/ppc: Add pcr_supported to POWER9 cpu class definitionSuraj Jitindar Singh2-0/+3
2017-01-31powerpc/cpu-models: rename ISAv3.00 logical PVR definitionSuraj Jitindar Singh1-1/+1
2017-01-31target-ppc: Add xvcv[hpsp, sphp] instructionsNikunj A Dadhania4-9/+24
2017-01-31target-ppc: Add xsmulqp instructionBharata B Rao4-0/+38
2017-01-31target-ppc: Add xsdivqp instructionBharata B Rao4-0/+39
2017-01-31target-ppc: Add xscvsdqp and xscvudqp instructionsBharata B Rao4-0/+31
2017-01-31target-ppc: Use ppc_vsr_t.f128 in xscmp[o,u,exp]qpBharata B Rao1-12/+8
2017-01-31ppc: Implement bcdutrunc. instructionJose Ricardo Ziviani4-1/+57
2017-01-31ppc: Implement bcdtrunc. instructionJose Ricardo Ziviani4-2/+45
2017-01-31target-ppc: Add xscvqps[d,w]z instructionsBharata B Rao4-0/+46
2017-01-31target-ppc: Add xvxsigdp instructionNikunj A Dadhania2-0/+41
2017-01-31target-ppc: Add xvxsigsp instructionNikunj A Dadhania4-0/+24
2017-01-31target-ppc: Add xvxexpdp instructionNikunj A Dadhania2-0/+18
2017-01-31target-ppc: Add xvxexpsp instructionNikunj A Dadhania2-0/+18
2017-01-31target-ppc: Add xviexpdp instructionNikunj A Dadhania2-0/+27
2017-01-31target-ppc: Add xviexpsp instructionNikunj A Dadhania2-0/+28
2017-01-31target-ppc: Add xsiexpqp instructionNikunj A Dadhania2-0/+23
2017-01-31target-ppc: Add xsiexpdp instructionNikunj A Dadhania2-0/+21
2017-01-31ppc: Implement bcdsr. instructionJose Ricardo Ziviani4-0/+52
2017-01-31ppc: Implement bcdus. instructionJose Ricardo Ziviani4-1/+46
2017-01-31ppc: Implement bcds. instructionJose Ricardo Ziviani4-1/+46
2017-01-31target-ppc: xscvqpdp zero VSRNikunj A Dadhania1-1/+1
2017-01-31ppc: Fix a warning in bcdcfz code and improve BCD_DIG_BYTE macroJose Ricardo Ziviani1-3/+3
2017-01-31target-ppc: Add xscvqpdp instructionBharata B Rao4-0/+31
2017-01-31target-ppc: Add xscvdpqp instructionBharata B Rao4-0/+48
2017-01-31target-ppc: Add xsaddqp instructionsBharata B Rao5-0/+41
2017-01-31ppc: Add ppc_set_compat_all()David Gibson2-0/+38
2017-01-31target-ppc: Add xsxsigqp instructionsNikunj A Dadhania2-0/+30
2017-01-31target-ppc: Add xsxsigdp instructionNikunj A Dadhania2-0/+30
2017-01-31target-ppc: Add xsxexpqp instructionNikunj A Dadhania2-0/+16
2017-01-31target-ppc: Add xsxexpdp instructionNikunj A Dadhania2-0/+17
2017-01-31target-ppc: Use correct precision for FPRF settingBharata B Rao2-2/+3
2017-01-31target-ppc: Add xscvdphp, xscvhpdpBharata B Rao5-0/+42
2017-01-31target-ppc: Rename helper_compute_fprf to helper_compute_fprf_float64Bharata B Rao3-70/+73
2017-01-31target-ppc: Replace isden by float64_is_zero_or_denormalBharata B Rao1-10/+1
2017-01-31target-ppc: Use float64 arg in helper_compute_fprf()Bharata B Rao1-9/+7
2017-01-31target-ppc: Add xxinsertw instructionNikunj A Dadhania4-2/+30
2017-01-31target-ppc: Add xxextractuw instructionNikunj A Dadhania4-0/+62
2017-01-31ppc: Validate compatibility modes when settingDavid Gibson2-0/+43
2017-01-31ppc: Rewrite ppc_get_compat_smt_threads()David Gibson3-21/+19
2017-01-31ppc: Rewrite ppc_set_compat()David Gibson4-43/+97
2017-01-31target-ppc: implement stxvll instructionsNikunj A Dadhania4-0/+4
2017-01-31target-ppc: implement stxvl instructionNikunj A Dadhania4-0/+34
2017-01-31target-ppc: implement lxvll instructionNikunj A Dadhania4-0/+4
2017-01-31target-ppc: implement lxvl instructionNikunj A Dadhania4-0/+70
2017-01-31target-ppc: Add xxperm and xxpermr instructionsBharata B Rao4-0/+29
2017-01-31target-ppc: implement xscpsgnqp instructionNikunj A Dadhania2-1/+12
2017-01-31target-ppc: implement xsnegqp instructionNikunj A Dadhania2-0/+5
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