riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2023-02-07	target/riscv: fix SBI getchar handler for KVM	Vladimir Isaev	1	-2/+3
2023-02-07	target/riscv: fix ctzw behavior	Vladimir Isaev	1	-0/+1
2023-02-07	target/riscv: fix for virtual instr exception	Deepak Gupta	1	-0/+1
2023-02-07	RISC-V: Adding XTheadFmv ISA extension	Christoph Müllner	5	-3/+55
2023-02-07	RISC-V: Add initial support for T-Head C906	Christoph Müllner	3	-0/+38
2023-02-07	RISC-V: Set minimum priv version for Zfh to 1.11	Christoph Müllner	1	-1/+1
2023-02-07	RISC-V: Adding T-Head FMemIdx extension	Christoph Müllner	5	-1/+123
2023-02-07	RISC-V: Adding T-Head MemIdx extension	Christoph Müllner	5	-1/+464
2023-02-07	RISC-V: Adding T-Head MemPair extension	Christoph Müllner	5	-1/+109
2023-02-07	RISC-V: Adding T-Head multiply-accumulate instructions	Christoph Müllner	5	-1/+96
2023-02-07	RISC-V: Adding XTheadCondMov ISA extension	Christoph Müllner	5	-1/+43
2023-02-07	RISC-V: Adding XTheadBs ISA extension	Christoph Müllner	5	-1/+23
2023-02-07	RISC-V: Adding XTheadBb ISA extension	Christoph Müllner	5	-2/+149
2023-02-07	RISC-V: Adding XTheadBa ISA extension	Christoph Müllner	5	-1/+66
2023-02-07	RISC-V: Adding XTheadSync ISA extension	Christoph Müllner	7	-1/+105
2023-02-07	RISC-V: Adding XTheadCmo ISA extension	Christoph Müllner	6	-0/+131
2023-02-07	target/riscv: set tval for triggered watchpoints	Sergey Matyukevich	2	-1/+6
2023-02-07	target/riscv: Ensure opcode is saved for all relevant instructions	Anup Patel	7	-3/+21
2023-02-07	target/riscv: No need to re-start QEMU timer when timecmp == UINT64_MAX	Anup Patel	1	-0/+24
2023-02-07	target/riscv: Don't clear mask in riscv_cpu_update_mip() for VSTIP	Anup Patel	2	-6/+8
2023-02-07	target/riscv: Update VS timer whenever htimedelta changes	Anup Patel	1	-0/+16
2023-02-04	Merge tag 'pull-tcg-20230204' of https://gitlab.com/rth7680/qemu into staging	Peter Maydell	15	-771/+483
2023-02-04	target/i386: Inline cmpxchg16b	Richard Henderson	3	-78/+39
2023-02-04	target/i386: Inline cmpxchg8b	Richard Henderson	3	-64/+49
2023-02-04	target/i386: Split out gen_cmpxchg8b, gen_cmpxchg16b	Richard Henderson	1	-17/+31
2023-02-04	target/s390x: Implement CC_OP_NZ in gen_op_calc_cc	Richard Henderson	1	-0/+3
2023-02-04	target/s390x: Use tcg_gen_atomic_cmpxchg_i128 for CDSG	Richard Henderson	4	-78/+33
2023-02-04	target/s390x: Use Int128 for passing float128	Richard Henderson	4	-105/+121
2023-02-04	target/s390x: Use Int128 for returning float128	Richard Henderson	4	-59/+63
2023-02-04	target/s390x: Copy wout_x1 to wout_x1_P	Richard Henderson	2	-6/+14
2023-02-04	target/s390x: Use Int128 for return from TRE	Richard Henderson	3	-7/+9
2023-02-04	target/s390x: Use Int128 for return from CKSM	Richard Henderson	3	-7/+8
2023-02-04	target/s390x: Use Int128 for return from CLST	Richard Henderson	3	-10/+11
2023-02-04	target/s390x: Use a single return for helper_divs64/u64	Richard Henderson	3	-35/+21
2023-02-04	target/s390x: Use a single return for helper_divs32/u32	Richard Henderson	3	-18/+18
2023-02-04	target/ppc: Use tcg_gen_atomic_cmpxchg_i128 for STQCX	Richard Henderson	3	-101/+47
2023-02-04	target/arm: Use tcg_gen_atomic_cmpxchg_i128 for CASP	Richard Henderson	3	-89/+19
2023-02-04	target/arm: Use tcg_gen_atomic_cmpxchg_i128 for STXP	Richard Henderson	3	-135/+35
2023-02-04	Merge tag 'm68k-next-pull-request' of https://github.com/vivier/qemu-m68k int...	Peter Maydell	1	-0/+4
2023-02-03	target/arm: Enable FEAT_FGT on '-cpu max'	Peter Maydell	1	-0/+1
2023-02-03	target/arm: Implement MDCR_EL2.TDCC and MDCR_EL3.TDCC traps	Peter Maydell	1	-4/+31
2023-02-03	target/arm: Implement the HFGITR_EL2.SVC_EL0 and SVC_EL1 traps	Peter Maydell	5	-4/+40
2023-02-03	target/arm: Implement the HFGITR_EL2.ERET trap	Peter Maydell	5	-0/+26
2023-02-03	target/arm: Mark up sysregs for HFGITR bits 48..63	Peter Maydell	2	-0/+13
2023-02-03	target/arm: Mark up sysregs for HFGITR bits 18..47	Peter Maydell	2	-0/+60
2023-02-03	target/arm: Mark up sysregs for HFGITR bits 12..17	Peter Maydell	2	-0/+12
2023-02-03	target/arm: Mark up sysregs for HFGITR bits 0..11	Peter Maydell	2	-0/+42
2023-02-03	target/arm: Mark up sysregs for HDFGRTR bits 12..63	Peter Maydell	2	-0/+49
2023-02-03	target/arm: Mark up sysregs for HDFGRTR bits 0..11	Peter Maydell	2	-0/+23
2023-02-03	target/arm: Mark up sysregs for HFGRTR bits 36..63	Peter Maydell	2	-0/+17