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authorPeter Maydell <peter.maydell@linaro.org>2023-01-30 18:24:59 +0000
committerPeter Maydell <peter.maydell@linaro.org>2023-02-03 12:59:24 +0000
commitbb18151d8bd9bedc497ee9d4e8d81b39a4e5bbf6 (patch)
tree1f501762586199d6ca773a85e62a1f978c97d755 /target
parent1748ef03c562dd4e5222e6d665142b25c0cfb1d1 (diff)
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target/arm: Enable FEAT_FGT on '-cpu max'
Update the ID registers for TCG's '-cpu max' to report the presence of FEAT_FGT Fine-Grained Traps support. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Fuad Tabba <tabba@google.com> Message-id: 20230130182459.3309057-24-peter.maydell@linaro.org Message-id: 20230127175507.2895013-24-peter.maydell@linaro.org
Diffstat (limited to 'target')
-rw-r--r--target/arm/cpu64.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 0e02196..4066950 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -1224,6 +1224,7 @@ static void aarch64_max_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 2); /* 16k stage2 supported */
t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN64_2, 2); /* 64k stage2 supported */
t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 2); /* 4k stage2 supported */
+ t = FIELD_DP64(t, ID_AA64MMFR0, FGT, 1); /* FEAT_FGT */
cpu->isar.id_aa64mmfr0 = t;
t = cpu->isar.id_aa64mmfr1;