riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2024-03-12	target: Replace CPU_GET_CLASS(cpu -> obj) in cpu_reset_hold() handler	Philippe Mathieu-Daudé	18	-51/+51
2024-03-12	bulk: Call in place single use cpu_env()	Philippe Mathieu-Daudé	7	-27/+13
2024-03-12	bulk: Access existing variables initialized to &S->F when available	Philippe Mathieu-Daudé	6	-12/+12
2024-03-12	target/s390x/cpu_models: Fix missing ERRP_GUARD() for error_prepend()	Zhao Liu	1	-0/+2
2024-03-09	Merge tag 'hw-misc-20240309' of https://github.com/philmd/qemu into staging	Peter Maydell	1	-0/+1
2024-03-09	target/i386/sev: Fix missing ERRP_GUARD() for error_prepend()	Zhao Liu	1	-0/+1
2024-03-09	Merge tag 'pull-hv-balloon-20240308' of https://github.com/maciejsszmigiero/q...	Peter Maydell	4	-0/+18
2024-03-08	Merge tag 'pull-target-arm-20240308' of https://git.linaro.org/people/pmaydel...	Peter Maydell	11	-434/+683
2024-03-08	target/arm: Move v7m-related code from cpu32.c into a separate file	Thomas Huth	4	-261/+296
2024-03-08	vmbus: Print a warning when enabled without the recommended set of features	Maciej S. Szmigiero	4	-0/+18
2024-03-08	target/riscv: Fix privilege mode of G-stage translation for debugging	Hiroaki Yamamoto	1	-1/+1
2024-03-08	target/riscv: Fix shift count overflow	demin.han	1	-3/+2
2024-03-08	trans_rvv.c.inc: remove 'is_store' bool from load/store fns	Daniel Henrique Barboza	1	-29/+29
2024-03-08	trans_rvv.c.inc: mark_vs_dirty() before loads and stores	Daniel Henrique Barboza	1	-15/+8
2024-03-08	target/riscv: mcountinhibit, mcounteren, scounteren, hcounteren is 32-bit	Vadim Shakirov	2	-12/+12
2024-03-08	target/riscv: move ratified/frozen exts to non-experimental	Daniel Henrique Barboza	1	-13/+9
2024-03-08	target/riscv/kvm: update KVM exts to Linux 6.8	Daniel Henrique Barboza	1	-0/+29
2024-03-08	RISC-V: Add support for Ztso	Palmer Dabbelt	6	-5/+48
2024-03-08	target/riscv: Add missing include guard in pmu.h	Frank Chang	1	-0/+5
2024-03-08	target/riscv: UPDATE xATP write CSR	Irina Ryapolova	1	-23/+29
2024-03-08	target/riscv: FIX xATP_MODE validation	Irina Ryapolova	1	-2/+2
2024-03-08	target/riscv: Promote svade to a normal extension	Andrew Jones	2	-7/+8
2024-03-08	target/riscv: Gate hardware A/D PTE bit updating	Andrew Jones	3	-15/+22
2024-03-08	target/riscv: Reset henvcfg to zero	Andrew Jones	2	-3/+2
2024-03-08	target/riscv: add remaining named features	Daniel Henrique Barboza	3	-7/+43
2024-03-08	target/riscv: add riscv,isa to named features	Daniel Henrique Barboza	3	-16/+23
2024-03-08	target/riscv/tcg: set 'mmu' with 'satp' in cpu_set_profile()	Daniel Henrique Barboza	1	-0/+1
2024-03-08	target/riscv: Update $ra with current $pc in trans_cm_jalt()	Jason Chien	1	-1/+5
2024-03-07	target/arm: Fix 32-bit SMOPA	Richard Henderson	1	-33/+46
2024-03-07	target/arm: Enable FEAT_ECV for 'max' CPU	Peter Maydell	1	-0/+1
2024-03-07	target/arm: Implement FEAT_ECV CNTPOFF_EL2 handling	Peter Maydell	4	-2/+73
2024-03-07	target/arm: Define CNTPCTSS_EL0 and CNTVCTSS_EL0	Peter Maydell	1	-0/+43
2024-03-07	target/arm: Implement new FEAT_ECV trap bits	Peter Maydell	2	-5/+51
2024-03-07	target/arm: Don't allow RES0 CNTHCTL_EL2 bits to be written	Peter Maydell	1	-0/+18
2024-03-07	target/arm: use FIELD macro for CNTHCTL bit definitions	Peter Maydell	2	-7/+29
2024-03-07	target/arm: Timer _EL02 registers UNDEF for E2H == 0	Peter Maydell	1	-1/+1
2024-03-07	target/arm: Move some register related defines to internals.h	Peter Maydell	2	-128/+128
2024-03-06	target/loongarch: honour show_opcodes when disassembling	Alex Bennée	1	-4/+9
2024-03-05	target/arm: Do memory type alignment check when translation enabled	Richard Henderson	1	-0/+39
2024-03-05	target/arm: Do memory type alignment check when translation disabled	Richard Henderson	1	-2/+32
2024-03-05	accel/tcg: Add tlb_fill_flags to CPUTLBEntryFull	Richard Henderson	1	-1/+1
2024-03-05	target/arm: Support 32-byte alignment in pow2_align	Richard Henderson	1	-7/+1
2024-03-05	Merge tag 'pull-tcg-20240301' of https://gitlab.com/rth7680/qemu into staging	Peter Maydell	4	-26/+56
2024-03-03	target/hppa: Restore unwind_breg before calculating ior	Helge Deller	3	-3/+6
2024-03-03	target: hppa: Fix unaligned double word accesses for hppa64	Guenter Roeck	1	-1/+2
2024-02-29	target/alpha: Enable TARGET_PAGE_BITS_VARY for user-only	Richard Henderson	1	-2/+14
2024-02-29	target/ppc: Enable TARGET_PAGE_BITS_VARY for user-only	Richard Henderson	1	-1/+8
2024-02-29	target/arm: Enable TARGET_PAGE_BITS_VARY for AArch64 user-only	Richard Henderson	2	-23/+34
2024-02-28	Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging	Peter Maydell	5	-45/+92
2024-02-28	gdbstub: Add members to identify registers to GDBFeature	Akihiko Odaki	1	-3/+1