riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2021-04-30	target/arm: Enforce alignment for SRS	Richard Henderson	1	-2/+2
2021-04-30	target/arm: Enforce alignment for RFE	Richard Henderson	1	-2/+2
2021-04-30	target/arm: Enforce alignment for LDM/STM	Richard Henderson	1	-2/+2
2021-04-30	target/arm: Enforce alignment for LDA/LDAH/STL/STLH	Richard Henderson	1	-2/+2
2021-04-30	target/arm: Enforce word alignment for LDRD/STRD	Richard Henderson	1	-8/+8
2021-04-30	target/arm: Adjust gen_aa32_{ld, st}_i64 for align+endianness	Richard Henderson	2	-35/+49
2021-04-30	target/arm: Fix SCTLR_B test for TCGv_i64 load/store	Richard Henderson	1	-2/+2
2021-04-30	target/arm: Merge gen_aa32_frob64 into gen_aa32_ld_i64	Richard Henderson	1	-20/+15
2021-04-30	target/arm: Adjust gen_aa32_{ld, st}_i32 for align+endianness	Richard Henderson	3	-52/+77
2021-04-30	target/arm: Add ALIGN_MEM to TBFLAG_ANY	Richard Henderson	5	-6/+25
2021-04-30	target/arm: Move TBFLAG_ANY bits to the bottom	Richard Henderson	1	-7/+7
2021-04-30	target/arm: Move TBFLAG_AM32 bits to the top	Richard Henderson	1	-21/+21
2021-04-30	target/arm: Move mode specific TB flags to tb->cs_base	Richard Henderson	3	-26/+35
2021-04-30	target/arm: Introduce CPUARMTBFlags	Richard Henderson	5	-37/+57
2021-04-30	target/arm: Add wrapper macros for accessing tbflags	Richard Henderson	5	-92/+101
2021-04-30	target/arm: Rename TBFLAG_ANY, PSTATE_SS	Richard Henderson	4	-5/+5
2021-04-30	target/arm: Rename TBFLAG_A32, SCTLR_B	Richard Henderson	3	-3/+3
2021-04-30	target/arm: Fix decode of align in VLDST_single	Richard Henderson	2	-4/+4
2021-04-30	target/arm: Remove log2_esize parameter to gen_mte_checkN	Richard Henderson	3	-11/+10
2021-04-30	target/arm: Simplify sve mte checking	Richard Henderson	1	-58/+26
2021-04-30	target/arm: Rename mte_probe1 to mte_probe	Richard Henderson	3	-7/+7
2021-04-30	target/arm: Merge mte_check1, mte_checkN	Richard Henderson	5	-38/+14
2021-04-30	target/arm: Replace MTEDESC ESIZE+TSIZE with SIZEM1	Richard Henderson	4	-18/+14
2021-04-30	target/arm: Fix unaligned checks for mte_check1, mte_probe1	Richard Henderson	1	-74/+35
2021-04-30	target/arm: Split out mte_probe_int	Richard Henderson	1	-12/+40
2021-04-30	target/arm: Fix mte_checkN	Richard Henderson	1	-22/+18
2021-04-30	target/arm: Make Thumb store insns UNDEF for Rn==1111	Peter Maydell	1	-0/+16
2021-04-23	target/s390x: fix s390_probe_access to check PAGE_WRITE_ORG for writeability	Alex Bennée	1	-1/+1
2021-04-20	target/mips/rel6_translate: Change license to GNU LGPL v2.1 (or later)	Philippe Mathieu-Daudé	1	-5/+4
2021-04-17	target/arm: drop CF_LAST_IO/dc->condjump check	Alex Bennée	1	-5/+0
2021-04-13	target/mips: Fix TCG temporary leak in gen_cache_operation()	Philippe Mathieu-Daudé	1	-0/+2
2021-04-12	target/arm: Check PAGE_WRITE_ORG for MTE writeability	Richard Henderson	1	-1/+1
2021-04-09	i386: Add missing cpu feature bits in EPYC-Rome model	Babu Moger	1	-0/+12
2021-04-06	Revert "target/arm: Make number of counters in PMCR follow the CPU"	Peter Maydell	5	-28/+12
2021-04-05	target/alpha: fix icount handling for timer instructions	Pavel Dovgalyuk	1	-2/+7
2021-04-04	Merge remote-tracking branch 'remotes/xtensa/tags/20210403-xtensa' into staging	Peter Maydell	2	-12/+5
2021-04-03	target/xtensa: make xtensa_modules static on import	Max Filippov	1	-0/+1
2021-04-03	target/xtensa: fix meson.build rule for xtensa cores	Max Filippov	2	-12/+4
2021-04-01	hexagon: do not specify Python scripts as inputs	Paolo Bonzini	1	-20/+10
2021-04-01	hexagon: do not specify executables as inputs	Paolo Bonzini	1	-4/+2
2021-04-01	target/openrisc: fix icount handling for timer instructions	Pavel Dovgalyuk	1	-0/+15
2021-04-01	target/i386: Verify memory operand for lcall and ljmp	Richard Henderson	1	-0/+6
2021-03-31	target/ppc/kvm: Cache timebase frequency	Greg Kurz	1	-6/+19
2021-03-30	target/arm: Make number of counters in PMCR follow the CPU	Peter Maydell	5	-12/+28
2021-03-26	s390x: move S390_ADAPTER_SUPPRESSIBLE	Gerd Hoffmann	1	-3/+6
2021-03-23	Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210323'...	Peter Maydell	2	-1/+2
2021-03-23	target/arm: Set ARMMMUFaultInfo.level in user-only arm_cpu_tlb_fill	Richard Henderson	1	-0/+1
2021-03-23	target/arm: Make M-profile VTOR loads on reset handle memory aliasing	Peter Maydell	1	-1/+1
2021-03-22	target/riscv: Prevent lost illegal instruction exceptions	Georg Kotheimer	1	-178/+1
2021-03-22	target/riscv: Add proper two-stage lookup exception detection	Georg Kotheimer	3	-13/+13