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2020-08-25target/riscv: Support the Virtual Instruction faultAlistair Francis5-6/+109
2020-08-25target/riscv: Return the exception from invalid CSR accessesAlistair Francis2-29/+35
2020-08-25target/riscv: Support the v0.6 Hypervisor extension CRSsAlistair Francis2-0/+43
2020-08-25target/riscv: Only support little endian guestsAlistair Francis1-0/+5
2020-08-25target/riscv: Only support a single VSXL lengthAlistair Francis1-0/+9
2020-08-25target/riscv: Update the CSRs to the v0.6 Hyp extensionAlistair Francis1-6/+8
2020-08-25target/riscv: Update the Hypervisor trap return/entryAlistair Francis4-26/+9
2020-08-25target/riscv: Fix the interrupt cause codeAlistair Francis1-2/+3
2020-08-25target/riscv: Convert MSTATUS MTL to GVAAlistair Francis3-9/+26
2020-08-25target/riscv: Don't allow guest to write to htinstAlistair Francis1-1/+0
2020-08-25target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructionsAlistair Francis1-35/+25
2020-08-25target/riscv: Allow generating hlv/hlvx/hsv instructionsAlistair Francis6-0/+474
2020-08-25target/riscv: Allow setting a two-stage lookup in the virt statusAlistair Francis3-0/+21
2020-08-24Merge remote-tracking branch 'remotes/xtensa/tags/20200821-xtensa' into stagingPeter Maydell19-415/+197691
2020-08-24Merge remote-tracking branch 'remotes/edgar/tags/edgar/xilinx-next-2020-08-24...Peter Maydell1-10/+28
2020-08-24Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200824'...Peter Maydell16-265/+437
2020-08-24target/arm: Use correct FPST for VCMLA, VCADD on fp16Peter Maydell1-3/+3
2020-08-24target/arm: Implement FPST_STD_F16 fpstatusPeter Maydell4-2/+18
2020-08-24target/arm: Make A32/T32 use new fpstatus_ptr() APIPeter Maydell3-49/+36
2020-08-24target/arm: Replace A64 get_fpstatus_ptr() with generic fpstatus_ptr()Peter Maydell4-72/+103
2020-08-24target/arm: Delete unused ARM_FEATURE_CRCPeter Maydell1-1/+0
2020-08-24target/arm/translate.c: Delete/amend incorrect commentsPeter Maydell1-2/+2
2020-08-24target/arm: Delete unused VFP_DREG macrosPeter Maydell1-15/+0
2020-08-24target/arm: Remove ARCH macroPeter Maydell1-5/+9
2020-08-24target/arm: Convert T32 coprocessor insns to decodetreePeter Maydell2-62/+21
2020-08-24target/arm: Do M-profile NOCP checks early and via decodetreePeter Maydell5-27/+100
2020-08-24target/arm: Tidy up disas_arm_insn()Peter Maydell1-17/+9
2020-08-24target/arm: Convert A32 coprocessor insns to decodetreePeter Maydell3-11/+111
2020-08-24target/arm: Separate decode from handling of coproc insnsPeter Maydell1-32/+44
2020-08-24target/arm: Pull handling of XScale insns out of disas_coproc_insn()Peter Maydell1-15/+29
2020-08-24target/microblaze: mbar: Trap sleeps from user-spaceEdgar E. Iglesias1-0/+5
2020-08-24target/microblaze: swx: Use atomic_cmpxchgEdgar E. Iglesias1-8/+13
2020-08-24target/microblaze: mbar: Add support for data-access barriersEdgar E. Iglesias1-0/+5
2020-08-24target/microblaze: mbar: Move LOG_DIS to before sleepEdgar E. Iglesias1-1/+2
2020-08-24target/microblaze: mbar: Transfer dc->rd to mbar_immEdgar E. Iglesias1-2/+4
2020-08-24Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-5.2-20200818' into...Peter Maydell8-54/+197
2020-08-23Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20200...Peter Maydell8-83/+245
2020-08-21target/riscv: Change the TLB page size depends on PMP entries.Zong Li3-2/+62
2020-08-21target/riscv: Fix the translation of physical addressZong Li1-2/+3
2020-08-21riscv: Fix bug in setting pmpcfg CSR for RISCV64Hou Weiying1-3/+2
2020-08-21target/riscv: check before allocating TCG tempsLIU Zhiwei2-8/+8
2020-08-21target/riscv: Clean up fmv.w.xLIU Zhiwei1-5/+1
2020-08-21target/riscv: Check nanboxed inputs in trans_rvf.inc.cRichard Henderson2-16/+73
2020-08-21target/riscv: Check nanboxed inputs to fp helpersRichard Henderson2-18/+57
2020-08-21target/riscv: Generate nanboxed results from trans_rvf.inc.cRichard Henderson1-0/+4
2020-08-21target/riscv: Generalize gen_nanbox_fpr to gen_nanbox_sRichard Henderson2-15/+12
2020-08-21target/riscv: Generate nanboxed results from fp helpersRichard Henderson2-19/+28
2020-08-21target/xtensa: import DSP3400 coreMax Filippov6-0/+173129
2020-08-21target/xtensa: import de233_fpu coreMax Filippov6-0/+22538
2020-08-21target/xtensa: implement FPU division and square rootMax Filippov3-0/+132