riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2023-05-13	Merge tag 'or1k-pull-request-20230513' of https://github.com/stffrdhrn/qemu i...	Richard Henderson	4	-53/+81
2023-05-12	target/arm: Correct AArch64.S2MinTxSZ 32-bit EL1 input size check	Peter Maydell	5	-19/+30
2023-05-12	target/arm: Select CONFIG_ARM_V7M when TCG is enabled	Fabiano Rosas	1	-0/+1
2023-05-12	target/arm: Select SEMIHOSTING when using TCG	Fabiano Rosas	1	-7/+1
2023-05-12	target/arm: Fix handling of SW and NSW bits for stage 2 walks	Peter Maydell	1	-25/+51
2023-05-12	target/arm: Don't allow stage 2 page table walks to downgrade to NS	Peter Maydell	1	-2/+3
2023-05-12	target/arm: Move helper-{a64,mve,sme,sve}.h to tcg/	Richard Henderson	5	-4/+4
2023-05-12	target/arm: Move translate-a32.h, arm_ldst.h, sve_ldst_internal.h to tcg/	Richard Henderson	3	-0/+0
2023-05-11	target/openrisc: Setup FPU for detecting tininess before rounding	Stafford Horne	1	-0/+4
2023-05-11	target/openrisc: Set PC to cpu state on FPU exception	Stafford Horne	1	-2/+11
2023-05-11	target/openrisc: Allow fpcsr access in user mode	Stafford Horne	2	-51/+66
2023-05-11	target/loongarch: Do not include tcg-ldst.h	Richard Henderson	2	-2/+0
2023-05-11	target/sh4: Use MO_ALIGN where required	Richard Henderson	1	-36/+66
2023-05-11	target/nios2: Remove TARGET_ALIGNED_ONLY	Richard Henderson	1	-0/+10
2023-05-11	target/mips: Use MO_ALIGN instead of 0	Richard Henderson	1	-1/+1
2023-05-11	target/mips: Add missing default_tcg_memop_mask	Richard Henderson	4	-28/+42
2023-05-11	target/mips: Add MO_ALIGN to gen_llwp, gen_scwp	Richard Henderson	1	-2/+3
2023-05-11	target/m68k: Fix gen_load_fp for OS_LONG	Richard Henderson	1	-0/+1
2023-05-10	target/loongarch: Terminate vmstate subsections list	Richard Henderson	1	-0/+1
2023-05-08	target/i386: Add EPYC-Genoa model to support Zen 4 processor series	Babu Moger	1	-0/+122
2023-05-08	target/i386: Add VNMI and automatic IBRS feature bits	Babu Moger	2	-2/+5
2023-05-08	target/i386: Add missing feature bits in EPYC-Milan model	Babu Moger	1	-0/+70
2023-05-08	target/i386: Add feature bits for CPUID_Fn80000021_EAX	Babu Moger	2	-0/+32
2023-05-08	target/i386: Add a couple of feature bits in 8000_0008_EBX	Babu Moger	2	-2/+6
2023-05-08	target/i386: Add new EPYC CPU versions with updated cache_info	Michael Roth	1	-0/+118
2023-05-08	target/i386: allow versioned CPUs to specify new cache_info	Michael Roth	1	-3/+32
2023-05-06	Merge tag 'pull-loongarch-20230506' of https://gitlab.com/gaosong/qemu into s...	Richard Henderson	18	-55/+9986
2023-05-06	target/loongarch: CPUCFG support LSX	Song Gao	1	-0/+1
2023-05-06	target/loongarch: Use {set/get}_gpr replace to cpu_fpr	Song Gao	5	-43/+129
2023-05-06	target/loongarch: Implement vldi	Song Gao	3	-0/+148
2023-05-06	target/loongarch: Implement vld vst	Song Gao	4	-0/+239
2023-05-06	target/loongarch: Implement vilvl vilvh vextrins vshuf	Song Gao	5	-0/+248
2023-05-06	target/loongarch: Implement vreplve vpack vpick	Song Gao	5	-0/+319
2023-05-06	target/loongarch: Implement vinsgr2vr vpickve2gr vreplgr2vr	Song Gao	3	-0/+173
2023-05-06	target/loongarch: Implement vbitsel vset	Song Gao	5	-0/+174
2023-05-06	target/loongarch: Implement vfcmp	Song Gao	5	-0/+190
2023-05-06	target/loongarch: Implement vseq vsle vslt	Song Gao	5	-0/+332
2023-05-06	target/loongarch: Implement LSX fpu fcvt instructions	Song Gao	5	-0/+600
2023-05-06	target/loongarch: Implement LSX fpu arith instructions	Song Gao	8	-1/+377
2023-05-06	target/loongarch: Implement vfrstp	Song Gao	5	-0/+61
2023-05-06	target/loongarch: Implement vbitclr vbitset vbitrev	Song Gao	5	-0/+437
2023-05-06	target/loongarch: Implement vpcnt	Song Gao	5	-0/+38
2023-05-06	target/loongarch: Implement vclo vclz	Song Gao	5	-0/+67
2023-05-06	target/loongarch: Implement vssrlrn vssrarn	Song Gao	5	-0/+478
2023-05-06	target/loongarch: Implement vssrln vssran	Song Gao	5	-0/+499
2023-05-06	target/loongarch: Implement vsrlrn vsrarn	Song Gao	5	-0/+190
2023-05-06	target/loongarch: Implement vsrln vsran	Song Gao	5	-0/+179
2023-05-06	target/loongarch: Implement vsrlr vsrar	Song Gao	5	-0/+176
2023-05-06	target/loongarch: Implement vsllwil vextl	Song Gao	5	-0/+89
2023-05-06	target/loongarch: Implement vsll vsrl vsra vrotr	Song Gao	3	-0/+108