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| author | Song Gao <gaosong@loongson.cn> | 2023-05-04 20:27:48 +0800 |
|---|---|---|
| committer | Song Gao <gaosong@loongson.cn> | 2023-05-06 11:19:47 +0800 |
| commit | b281d6961d5f31d1bbcfc2cd50d2a7237ee9d062 (patch) | |
| tree | bfd3bdb8645ef968b731c4eb2c5f3a9d71608c87 /target | |
| parent | f205a539f6b911f96f1010361f23a77d9c9f94ca (diff) | |
| download | qemu-b281d6961d5f31d1bbcfc2cd50d2a7237ee9d062.zip qemu-b281d6961d5f31d1bbcfc2cd50d2a7237ee9d062.tar.gz qemu-b281d6961d5f31d1bbcfc2cd50d2a7237ee9d062.tar.bz2 | |
target/loongarch: Implement vsll vsrl vsra vrotr
This patch includes:
- VSLL[I].{B/H/W/D};
- VSRL[I].{B/H/W/D};
- VSRA[I].{B/H/W/D};
- VROTR[I].{B/H/W/D}.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-23-gaosong@loongson.cn>
Diffstat (limited to 'target')
| -rw-r--r-- | target/loongarch/disas.c | 36 | ||||
| -rw-r--r-- | target/loongarch/insn_trans/trans_lsx.c.inc | 36 | ||||
| -rw-r--r-- | target/loongarch/insns.decode | 36 |
3 files changed, 108 insertions, 0 deletions
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c index eca0a4b..f7d0fb4 100644 --- a/target/loongarch/disas.c +++ b/target/loongarch/disas.c @@ -1103,3 +1103,39 @@ INSN_LSX(vandi_b, vv_i) INSN_LSX(vori_b, vv_i) INSN_LSX(vxori_b, vv_i) INSN_LSX(vnori_b, vv_i) + +INSN_LSX(vsll_b, vvv) +INSN_LSX(vsll_h, vvv) +INSN_LSX(vsll_w, vvv) +INSN_LSX(vsll_d, vvv) +INSN_LSX(vslli_b, vv_i) +INSN_LSX(vslli_h, vv_i) +INSN_LSX(vslli_w, vv_i) +INSN_LSX(vslli_d, vv_i) + +INSN_LSX(vsrl_b, vvv) +INSN_LSX(vsrl_h, vvv) +INSN_LSX(vsrl_w, vvv) +INSN_LSX(vsrl_d, vvv) +INSN_LSX(vsrli_b, vv_i) +INSN_LSX(vsrli_h, vv_i) +INSN_LSX(vsrli_w, vv_i) +INSN_LSX(vsrli_d, vv_i) + +INSN_LSX(vsra_b, vvv) +INSN_LSX(vsra_h, vvv) +INSN_LSX(vsra_w, vvv) +INSN_LSX(vsra_d, vvv) +INSN_LSX(vsrai_b, vv_i) +INSN_LSX(vsrai_h, vv_i) +INSN_LSX(vsrai_w, vv_i) +INSN_LSX(vsrai_d, vv_i) + +INSN_LSX(vrotr_b, vvv) +INSN_LSX(vrotr_h, vvv) +INSN_LSX(vrotr_w, vvv) +INSN_LSX(vrotr_d, vvv) +INSN_LSX(vrotri_b, vv_i) +INSN_LSX(vrotri_h, vv_i) +INSN_LSX(vrotri_w, vv_i) +INSN_LSX(vrotri_d, vv_i) diff --git a/target/loongarch/insn_trans/trans_lsx.c.inc b/target/loongarch/insn_trans/trans_lsx.c.inc index e5e1941..ad8f32e 100644 --- a/target/loongarch/insn_trans/trans_lsx.c.inc +++ b/target/loongarch/insn_trans/trans_lsx.c.inc @@ -2930,3 +2930,39 @@ static void do_vnori_b(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs, } TRANS(vnori_b, gvec_vv_i, MO_8, do_vnori_b) + +TRANS(vsll_b, gvec_vvv, MO_8, tcg_gen_gvec_shlv) +TRANS(vsll_h, gvec_vvv, MO_16, tcg_gen_gvec_shlv) +TRANS(vsll_w, gvec_vvv, MO_32, tcg_gen_gvec_shlv) +TRANS(vsll_d, gvec_vvv, MO_64, tcg_gen_gvec_shlv) +TRANS(vslli_b, gvec_vv_i, MO_8, tcg_gen_gvec_shli) +TRANS(vslli_h, gvec_vv_i, MO_16, tcg_gen_gvec_shli) +TRANS(vslli_w, gvec_vv_i, MO_32, tcg_gen_gvec_shli) +TRANS(vslli_d, gvec_vv_i, MO_64, tcg_gen_gvec_shli) + +TRANS(vsrl_b, gvec_vvv, MO_8, tcg_gen_gvec_shrv) +TRANS(vsrl_h, gvec_vvv, MO_16, tcg_gen_gvec_shrv) +TRANS(vsrl_w, gvec_vvv, MO_32, tcg_gen_gvec_shrv) +TRANS(vsrl_d, gvec_vvv, MO_64, tcg_gen_gvec_shrv) +TRANS(vsrli_b, gvec_vv_i, MO_8, tcg_gen_gvec_shri) +TRANS(vsrli_h, gvec_vv_i, MO_16, tcg_gen_gvec_shri) +TRANS(vsrli_w, gvec_vv_i, MO_32, tcg_gen_gvec_shri) +TRANS(vsrli_d, gvec_vv_i, MO_64, tcg_gen_gvec_shri) + +TRANS(vsra_b, gvec_vvv, MO_8, tcg_gen_gvec_sarv) +TRANS(vsra_h, gvec_vvv, MO_16, tcg_gen_gvec_sarv) +TRANS(vsra_w, gvec_vvv, MO_32, tcg_gen_gvec_sarv) +TRANS(vsra_d, gvec_vvv, MO_64, tcg_gen_gvec_sarv) +TRANS(vsrai_b, gvec_vv_i, MO_8, tcg_gen_gvec_sari) +TRANS(vsrai_h, gvec_vv_i, MO_16, tcg_gen_gvec_sari) +TRANS(vsrai_w, gvec_vv_i, MO_32, tcg_gen_gvec_sari) +TRANS(vsrai_d, gvec_vv_i, MO_64, tcg_gen_gvec_sari) + +TRANS(vrotr_b, gvec_vvv, MO_8, tcg_gen_gvec_rotrv) +TRANS(vrotr_h, gvec_vvv, MO_16, tcg_gen_gvec_rotrv) +TRANS(vrotr_w, gvec_vvv, MO_32, tcg_gen_gvec_rotrv) +TRANS(vrotr_d, gvec_vvv, MO_64, tcg_gen_gvec_rotrv) +TRANS(vrotri_b, gvec_vv_i, MO_8, tcg_gen_gvec_rotri) +TRANS(vrotri_h, gvec_vv_i, MO_16, tcg_gen_gvec_rotri) +TRANS(vrotri_w, gvec_vv_i, MO_32, tcg_gen_gvec_rotri) +TRANS(vrotri_d, gvec_vv_i, MO_64, tcg_gen_gvec_rotri) diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode index 6309683..7c0b0c4 100644 --- a/target/loongarch/insns.decode +++ b/target/loongarch/insns.decode @@ -803,3 +803,39 @@ vandi_b 0111 00111101 00 ........ ..... ..... @vv_ui8 vori_b 0111 00111101 01 ........ ..... ..... @vv_ui8 vxori_b 0111 00111101 10 ........ ..... ..... @vv_ui8 vnori_b 0111 00111101 11 ........ ..... ..... @vv_ui8 + +vsll_b 0111 00001110 10000 ..... ..... ..... @vvv +vsll_h 0111 00001110 10001 ..... ..... ..... @vvv +vsll_w 0111 00001110 10010 ..... ..... ..... @vvv +vsll_d 0111 00001110 10011 ..... ..... ..... @vvv +vslli_b 0111 00110010 11000 01 ... ..... ..... @vv_ui3 +vslli_h 0111 00110010 11000 1 .... ..... ..... @vv_ui4 +vslli_w 0111 00110010 11001 ..... ..... ..... @vv_ui5 +vslli_d 0111 00110010 1101 ...... ..... ..... @vv_ui6 + +vsrl_b 0111 00001110 10100 ..... ..... ..... @vvv +vsrl_h 0111 00001110 10101 ..... ..... ..... @vvv +vsrl_w 0111 00001110 10110 ..... ..... ..... @vvv +vsrl_d 0111 00001110 10111 ..... ..... ..... @vvv +vsrli_b 0111 00110011 00000 01 ... ..... ..... @vv_ui3 +vsrli_h 0111 00110011 00000 1 .... ..... ..... @vv_ui4 +vsrli_w 0111 00110011 00001 ..... ..... ..... @vv_ui5 +vsrli_d 0111 00110011 0001 ...... ..... ..... @vv_ui6 + +vsra_b 0111 00001110 11000 ..... ..... ..... @vvv +vsra_h 0111 00001110 11001 ..... ..... ..... @vvv +vsra_w 0111 00001110 11010 ..... ..... ..... @vvv +vsra_d 0111 00001110 11011 ..... ..... ..... @vvv +vsrai_b 0111 00110011 01000 01 ... ..... ..... @vv_ui3 +vsrai_h 0111 00110011 01000 1 .... ..... ..... @vv_ui4 +vsrai_w 0111 00110011 01001 ..... ..... ..... @vv_ui5 +vsrai_d 0111 00110011 0101 ...... ..... ..... @vv_ui6 + +vrotr_b 0111 00001110 11100 ..... ..... ..... @vvv +vrotr_h 0111 00001110 11101 ..... ..... ..... @vvv +vrotr_w 0111 00001110 11110 ..... ..... ..... @vvv +vrotr_d 0111 00001110 11111 ..... ..... ..... @vvv +vrotri_b 0111 00101010 00000 01 ... ..... ..... @vv_ui3 +vrotri_h 0111 00101010 00000 1 .... ..... ..... @vv_ui4 +vrotri_w 0111 00101010 00001 ..... ..... ..... @vv_ui5 +vrotri_d 0111 00101010 0001 ...... ..... ..... @vv_ui6 |