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AgeCommit message (Expand)AuthorFilesLines
2023-08-24include/exec: Replace target_ulong with abi_ptr in cpu_[st|ld]*()Anton Johansson1-3/+3
2023-07-25other architectures: spelling fixesMichael Tokarev1-2/+2
2023-06-26target: Widen pc/cs_base in cpu_get_tb_cpu_stateAnton Johansson1-2/+2
2023-06-05accel/tcg: Introduce translator_io_startRichard Henderson1-2/+0
2023-06-05tcg: Pass TCGHelperInfo to tcg_gen_callNRichard Henderson1-0/+5
2023-06-05target/*: Add missing includes of tcg/debug-assert.hRichard Henderson2-0/+2
2023-03-13target/rx: Avoid tcg_const_i32Richard Henderson1-16/+16
2023-03-13target/rx: Avoid tcg_const_i32 when new temp neededRichard Henderson1-6/+6
2023-03-13target/rx: Use cpu_psw_z as temp in flags computationRichard Henderson1-15/+13
2023-03-13target/rx: Use tcg_gen_abs_i32Richard Henderson1-11/+1
2023-03-13target/rx: Remove `NB_MMU_MODES` defineAnton Johansson1-2/+0
2023-03-07gdbstub: move register helpers into standalone includeAlex Bennée1-1/+1
2023-03-05target/rx: Drop tcg_temp_freeRichard Henderson1-84/+0
2023-03-01accel/tcg: Pass max_insn to gen_intermediate_code by pointerRichard Henderson1-1/+1
2023-03-01target/rx: Replace `tb_pc()` with `tb->pc`Anton Johansson1-1/+2
2023-02-27target/cpu: Restrict cpu_get_phys_page_debug() handlers to sysemuPhilippe Mathieu-Daudé2-3/+3
2022-12-16target/rx: Convert to 3-phase resetPeter Maydell2-7/+10
2022-10-26Merge tag 'pull-tcg-20221026' of https://gitlab.com/rth7680/qemu into stagingStefan Hajnoczi2-6/+10
2022-10-26target/rx: Convert to tcg_ops restore_state_to_opcRichard Henderson2-6/+10
2022-10-24treewide: Remove the unnecessary space before semicolonBin Meng1-2/+2
2022-10-04accel/tcg: Introduce tb_pc and log_pcRichard Henderson1-1/+1
2022-10-04hw/core: Add CPUClass.get_pcRichard Henderson1-0/+8
2022-09-06accel/tcg: Add pc and host_pc params to gen_intermediate_codeRichard Henderson1-2/+3
2022-04-21Merge tag 'pull-rx-20220421' of https://gitlab.com/rth7680/qemu into stagingRichard Henderson3-32/+39
2022-04-21target/rx: update PC correctly in wait instructionTomoaki Kawada1-1/+1
2022-04-21target/rx: set PSW.I when executing wait instructionTomoaki Kawada1-0/+1
2022-04-21target/rx: Swap stack pointers on clrpsw/setpsw instructionRichard Henderson1-1/+6
2022-04-21target/rx: Move DISAS_UPDATE check for write to PSWRichard Henderson1-10/+4
2022-04-21target/rx: Store PSW.U in tb->flagsRichard Henderson2-19/+24
2022-04-21target/rx: Put tb_flags into DisasContextRichard Henderson1-1/+3
2022-04-21compiler.h: replace QEMU_NORETURN with G_NORETURNMarc-André Lureau1-10/+12
2022-04-20exec/translator: Pass the locked filepointer to disas_log hookRichard Henderson1-3/+4
2022-04-06Remove qemu-common.h include from most unitsMarc-André Lureau2-2/+0
2022-04-06Move CPU softfloat unions to cpu-float.hMarc-André Lureau1-0/+1
2022-03-06target: Use ArchCPU as interface to target CPUPhilippe Mathieu-Daudé1-1/+1
2022-03-06target: Introduce and use OBJECT_DECLARE_CPU_TYPE() macroPhilippe Mathieu-Daudé2-4/+1
2022-03-06target: Use CPUArchState as interface to target-specific CPU statePhilippe Mathieu-Daudé2-3/+1
2022-02-21target/rx: Remove unused ENV_OFFSET definitionPhilippe Mathieu-Daudé1-2/+0
2021-12-15target/rx/cpu.h: Don't include qemu-common.hPeter Maydell1-1/+0
2021-10-15target/rx: Drop checks for singlestep_enabledRichard Henderson3-19/+2
2021-09-21include/exec: Move cpu_signal_handler declarationRichard Henderson1-4/+0
2021-09-14target/rx: Restrict cpu_exec_interrupt() handler to sysemuPhilippe Mathieu-Daudé3-1/+7
2021-07-21accel/tcg: Remove TranslatorOps.breakpoint_checkRichard Henderson1-14/+0
2021-07-12Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210710' into...Peter Maydell1-11/+1
2021-07-09target/rx: Use translator_use_goto_tbRichard Henderson1-10/+1
2021-07-09tcg: Avoid including 'trace-tcg.h' in target translate.cPhilippe Mathieu-Daudé1-1/+0
2021-07-09meson: Introduce target-specific KconfigPhilippe Mathieu-Daudé1-0/+2
2021-05-26hw/core: Constify TCGCPUOpsRichard Henderson1-1/+1
2021-05-26cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOpsPhilippe Mathieu-Daudé1-1/+1
2021-05-26cpu: Introduce SysemuCPUOps structurePhilippe Mathieu-Daudé1-0/+10