riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2024-10-31	target/riscv: Fix vcompress with rvv_ta_all_1s	Anton Blanchard	1	-1/+1
2024-10-31	target/riscv/kvm: clarify how 'riscv-aia' default works	Daniel Henrique Barboza	1	-10/+4
2024-10-31	target/riscv/kvm: set 'aia_mode' to default in error path	Daniel Henrique Barboza	1	-7/+15
2024-10-31	target/riscv: Expose zicfiss extension as a cpu property	Deepak Gupta	1	-0/+1
2024-10-30	target/riscv: compressed encodings for sspush and sspopchk	Deepak Gupta	1	-0/+4
2024-10-30	target/riscv: implement zicfiss instructions	Deepak Gupta	4	-2/+140
2024-10-30	target/riscv: update `decode_save_opc` to store extra word2	Deepak Gupta	11	-34/+35
2024-10-30	target/riscv: AMO operations always raise store/AMO fault	Deepak Gupta	4	-2/+30
2024-10-30	target/riscv: mmu changes for zicfiss shadow stack protection	Deepak Gupta	2	-14/+53
2024-10-30	target/riscv: tb flag for shadow stack instructions	Deepak Gupta	3	-0/+9
2024-10-30	target/riscv: introduce ssp and enabling controls for zicfiss	Deepak Gupta	6	-0/+111
2024-10-30	target/riscv: Add zicfiss extension	Deepak Gupta	3	-0/+25
2024-10-30	target/riscv: Expose zicfilp extension as a cpu property	Deepak Gupta	1	-0/+1
2024-10-30	target/riscv: zicfilp `lpad` impl and branch tracking	Deepak Gupta	3	-1/+60
2024-10-30	target/riscv: tracking indirect branches (fcfi) for zicfilp	Deepak Gupta	4	-0/+39
2024-10-30	target/riscv: additional code information for sw check	Deepak Gupta	3	-0/+6
2024-10-30	target/riscv: save and restore elp state on priv transitions	Deepak Gupta	3	-0/+72
2024-10-30	target/riscv: Introduce elp state and enabling controls for zicfilp	Deepak Gupta	7	-1/+68
2024-10-30	target/riscv: Add zicfilp extension	Deepak Gupta	3	-0/+7
2024-10-30	target/riscv: expose *envcfg csr and priv to qemu-user as well	Deepak Gupta	2	-4/+10
2024-10-30	target/riscv: Set vtype.vill on CPU reset	Rob Bradford	1	-0/+1
2024-10-30	target/riscv: Add max32 CPU for RV64 QEMU	LIU Zhiwei	2	-5/+8
2024-10-30	target/riscv: Enable RV32 CPU support in RV64 QEMU	TANG Tiancheng	1	-3/+13
2024-10-30	target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU	TANG Tiancheng	1	-2/+6
2024-10-30	target/riscv: Detect sxl to set bit width for RV32 in RV64	TANG Tiancheng	1	-5/+12
2024-10-30	target/riscv: Correct SXL return value for RV32 in RV64 QEMU	TANG Tiancheng	1	-1/+4
2024-10-30	target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32	TANG Tiancheng	1	-1/+1
2024-10-30	target/riscv/csr.c: Fix an access to VXSAT	Evgenii Prokopiev	1	-2/+2
2024-10-04	Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging	Peter Maydell	1	-2/+2
2024-10-03	kvm: Allow kvm_arch_get/put_registers to accept Error**	Julia Suvorova	1	-2/+2
2024-10-02	target/riscv/cpu_helper: Fix linking problem with semihosting disabled	Thomas Huth	2	-2/+4
2024-10-02	target/riscv32: Fix masking of physical address	Andrew Jones	1	-3/+3
2024-10-02	target: riscv: Add Svvptc extension support	Alexandre Ghiti	2	-0/+3
2024-10-02	target/riscv: Add textra matching condition for the triggers	Alvin Chang	2	-1/+47
2024-10-02	target/riscv: Preliminary textra trigger CSR writting support	Alvin Chang	2	-6/+73
2024-10-02	target/riscv/cpu.c: Add 'fcsr' register to QEMU log as a part of F extension	Maria Klauchek	1	-0/+6
2024-10-02	target/riscv: Stop timer with infinite timecmp	Andrew Jones	1	-0/+1
2024-10-02	target/riscv/kvm: Fix the group bit setting of AIA	Andrew Jones	1	-1/+3
2024-10-02	target: riscv: Enable Bit Manip for OpenTitan Ibex CPU	Alistair Francis	1	-0/+5
2024-10-02	target/riscv: fix za64rs enabling	Vladimir Isaev	1	-1/+1
2024-10-02	target/riscv/tcg/tcg-cpu.c: consider MISA bit choice in implied rule	Daniel Henrique Barboza	1	-3/+10
2024-10-02	target/riscv: Add a property to set vl to ceil(AVL/2)	Jason Chien	3	-0/+4
2024-09-28	Merge tag 'pull-request-2024-09-25' of https://gitlab.com/thuth/qemu into sta...	Peter Maydell	2	-3/+0
2024-09-24	target/riscv: remove break after g_assert_not_reached()	Pierrick Bouvier	2	-3/+0
2024-09-20	license: Update deprecated SPDX tag GPL-2.0+ to GPL-2.0-or-later	Philippe Mathieu-Daudé	1	-1/+1
2024-09-13	target/riscv: Remove the deprecated 'any' CPU type	Philippe Mathieu-Daudé	2	-29/+0
2024-08-06	target/riscv: Add asserts for out-of-bound access	Atish Patra	1	-0/+4
2024-08-06	target/riscv: Relax fld alignment requirement	LIU Zhiwei	1	-4/+14
2024-08-06	target/riscv: Add MXLEN check for F/D/Q applies to zama16b	LIU Zhiwei	1	-2/+6
2024-08-06	target/riscv: Remove redundant insn length check for zama16b	LIU Zhiwei	3	-6/+6