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| author | TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com> | 2024-09-19 13:50:43 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2024-10-30 11:22:07 +1000 |
| commit | 929e4277c128772bad41cc795995f754cb9991af (patch) | |
| tree | 72e8e960056f5d94f3e1ee5fc0a756be8cb0d2d1 /target/riscv | |
| parent | efd29e3398001c764fc9f0066ba1589e6ebc1043 (diff) | |
| download | qemu-929e4277c128772bad41cc795995f754cb9991af.zip qemu-929e4277c128772bad41cc795995f754cb9991af.tar.gz qemu-929e4277c128772bad41cc795995f754cb9991af.tar.bz2 | |
target/riscv: Correct SXL return value for RV32 in RV64 QEMU
Ensure that riscv_cpu_sxl returns MXL_RV32 when runningRV32 in an
RV64 QEMU.
Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Fixes: 05e6ca5e156 ("target/riscv: Ignore reserved bits in PTE for RV64")
Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240919055048.562-4-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv')
| -rw-r--r-- | target/riscv/cpu.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 1619c3a..a63a297 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -709,8 +709,11 @@ static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env) #ifdef CONFIG_USER_ONLY return env->misa_mxl; #else - return get_field(env->mstatus, MSTATUS64_SXL); + if (env->misa_mxl != MXL_RV32) { + return get_field(env->mstatus, MSTATUS64_SXL); + } #endif + return MXL_RV32; } #endif |