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| author | Deepak Gupta <debug@rivosinc.com> | 2024-10-08 15:49:55 -0700 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2024-10-30 11:22:08 +1000 |
| commit | 6031102401ae8a69a87b20fbec2aae666625d96a (patch) | |
| tree | c9f59a6c44a7339181e912d839027b33a0ab54ce /target/riscv | |
| parent | 53309be15619096b4ff2f05ec5e5d9b9bb6b6a82 (diff) | |
| download | qemu-6031102401ae8a69a87b20fbec2aae666625d96a.zip qemu-6031102401ae8a69a87b20fbec2aae666625d96a.tar.gz qemu-6031102401ae8a69a87b20fbec2aae666625d96a.tar.bz2 | |
target/riscv: additional code information for sw check
sw check exception support was recently added. This patch further augments
sw check exception by providing support for additional code which is
provided in *tval. Adds `sw_check_code` field in cpuarchstate. Whenever
sw check exception is raised *tval gets the value deposited in
`sw_check_code`.
Signed-off-by: Deepak Gupta <debug@rivosinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241008225010.1861630-6-debug@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv')
| -rw-r--r-- | target/riscv/cpu.h | 2 | ||||
| -rw-r--r-- | target/riscv/cpu_helper.c | 3 | ||||
| -rw-r--r-- | target/riscv/csr.c | 1 |
3 files changed, 6 insertions, 0 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 2170792a..67ce6e0 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -232,6 +232,8 @@ struct CPUArchState { /* elp state for zicfilp extension */ bool elp; + /* sw check code for sw check exception */ + target_ulong sw_check_code; #ifdef CONFIG_USER_ONLY uint32_t elf_flags; #endif diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 62f455d..fa4982e 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1775,6 +1775,9 @@ void riscv_cpu_do_interrupt(CPUState *cs) cs->watchpoint_hit = NULL; } break; + case RISCV_EXCP_SW_CHECK: + tval = env->sw_check_code; + break; default: break; } diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 02bcb8a..ec1e2af 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1377,6 +1377,7 @@ static const uint64_t all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS | (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | \ (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | \ (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) | \ + (1ULL << (RISCV_EXCP_SW_CHECK)) | \ (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | \ (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | \ (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | \ |