index
:
riscv-gnu-toolchain/qemu.git
block
master
stable-0.10
stable-0.11
stable-0.12
stable-0.13
stable-0.14
stable-0.15
stable-1.0
stable-1.1
stable-1.2
stable-1.3
stable-1.4
stable-1.5
stable-1.6
stable-1.7
stable-2.0
stable-2.1
stable-2.10
stable-2.11
stable-2.12
stable-2.2
stable-2.3
stable-2.4
stable-2.5
stable-2.6
stable-2.7
stable-2.8
stable-2.9
stable-3.0
stable-3.1
stable-4.0
stable-4.1
stable-4.2
stable-5.0
stable-6.0
stable-6.1
stable-7.2
stable-8.0
stable-8.1
stable-8.2
stable-9.0
stable-9.1
staging
staging-7.2
staging-8.0
staging-8.1
staging-8.2
staging-9.0
staging-9.1
Unnamed repository; edit this file 'description' to name the repository.
root
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
target
/
riscv
Age
Commit message (
Expand
)
Author
Files
Lines
2022-01-08
target/riscv: Implement the stval/mtval illegal instruction
Alistair Francis
3
-0
/
+8
2022-01-08
target/riscv: Fixup setting GVA
Alistair Francis
1
-15
/
+6
2022-01-08
target/riscv: Set the opcode in DisasContext
Alistair Francis
1
-0
/
+2
2022-01-08
target/riscv: actual functions to realize crs 128-bit insns
Frédéric Pétrot
3
-30
/
+175
2022-01-08
target/riscv: modification of the trans_csrxx for 128-bit support
Frédéric Pétrot
1
-43
/
+158
2022-01-08
target/riscv: helper functions to wrap calls to 128-bit csr insns
Frédéric Pétrot
4
-0
/
+69
2022-01-08
target/riscv: adding high part of some csrs
Frédéric Pétrot
2
-0
/
+6
2022-01-08
target/riscv: support for 128-bit M extension
Frédéric Pétrot
6
-13
/
+295
2022-01-08
target/riscv: support for 128-bit arithmetic instructions
Frédéric Pétrot
5
-49
/
+222
2022-01-08
target/riscv: support for 128-bit shift instructions
Frédéric Pétrot
4
-44
/
+270
2022-01-08
target/riscv: support for 128-bit U-type instructions
Frédéric Pétrot
2
-4
/
+25
2022-01-08
target/riscv: support for 128-bit bitwise instructions
Frédéric Pétrot
1
-2
/
+19
2022-01-08
target/riscv: accessors to registers upper part and 128-bit load/store
Frédéric Pétrot
4
-10
/
+163
2022-01-08
target/riscv: moving some insns close to similar insns
Frédéric Pétrot
1
-17
/
+17
2022-01-08
target/riscv: setup everything for rv64 to support rv128 execution
Frédéric Pétrot
3
-0
/
+26
2022-01-08
target/riscv: array for the 64 upper bits of 128-bit registers
Frédéric Pétrot
4
-1
/
+35
2022-01-08
target/riscv: separation of bitwise logic and arithmetic helpers
Frédéric Pétrot
3
-9
/
+36
2022-01-08
target/riscv: additional macros to check instruction support
Frédéric Pétrot
1
-4
/
+16
2022-01-08
exec/memop: Adding signedness to quad definitions
Frédéric Pétrot
4
-17
/
+17
2022-01-08
target/riscv: Fix position of 'experimental' comment
Philipp Tomsich
1
-1
/
+2
2022-01-08
target/riscv: rvv-1.0: Call the correct RVF/RVD check function for narrowing ...
Frank Chang
1
-8
/
+24
2022-01-08
target/riscv: rvv-1.0: Call the correct RVF/RVD check function for widening f...
Frank Chang
1
-9
/
+25
2022-01-08
target/riscv: rvv-1.0: Call the correct RVF/RVD check function for widening f...
Frank Chang
1
-4
/
+8
2022-01-08
target/riscv: Enable the Hypervisor extension by default
Alistair Francis
1
-1
/
+1
2022-01-08
target/riscv: Mark the Hypervisor extension as non experimental
Alistair Francis
1
-1
/
+1
2022-01-08
target/riscv/pmp: fix no pmp illegal intrs
Nikita Shubin
1
-1
/
+2
2021-12-20
target/riscv: Enable bitmanip Zb[abcs] instructions
Vineet Gupta
1
-4
/
+4
2021-12-20
target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructions
Frank Chang
2
-6
/
+13
2021-12-20
target/riscv: rvv-1.0: update opivv_vadc_check() comment
Frank Chang
1
-1
/
+1
2021-12-20
target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmo...
Frank Chang
4
-8
/
+8
2021-12-20
target/riscv: rvv-1.0: add vector unit-stride mask load/store insns
Frank Chang
4
-0
/
+67
2021-12-20
target/riscv: rvv-1.0: add evl parameter to vext_ldst_us()
Frank Chang
1
-18
/
+18
2021-12-20
target/riscv: rvv-1.0: add vsetivli instruction
Frank Chang
2
-0
/
+29
2021-12-20
target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11
Frank Chang
1
-2
/
+2
2021-12-20
target/riscv: rvv-1.0: floating-point reciprocal estimate instruction
Frank Chang
4
-0
/
+197
2021-12-20
target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruc...
Frank Chang
4
-0
/
+189
2021-12-20
target/riscv: gdb: support vector registers for rv64 & rv32
Hsiangkai Wang
3
-0
/
+187
2021-12-20
target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid
Frank Chang
1
-0
/
+22
2021-12-20
target/riscv: rvv-1.0: implement vstart CSR
Frank Chang
5
-103
/
+199
2021-12-20
target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits
Frank Chang
3
-4
/
+4
2021-12-20
target/riscv: rvv-1.0: narrowing floating-point/integer type-convert
Frank Chang
4
-44
/
+97
2021-12-20
target/riscv: add "set round to odd" rounding mode helper function
Frank Chang
4
-0
/
+14
2021-12-20
target/riscv: rvv-1.0: widening floating-point/integer type-convert
Frank Chang
4
-14
/
+63
2021-12-20
target/riscv: rvv-1.0: floating-point/integer type-convert instructions
Frank Chang
2
-36
/
+59
2021-12-20
target/riscv: introduce floating-point rounding mode enum
Frank Chang
3
-15
/
+24
2021-12-20
target/riscv: rvv-1.0: floating-point min/max instructions
Frank Chang
1
-12
/
+12
2021-12-20
target/riscv: rvv-1.0: remove integer extract instruction
Frank Chang
2
-24
/
+0
2021-12-20
target/riscv: rvv-1.0: remove vmford.vv and vmford.vf
Frank Chang
4
-17
/
+0
2021-12-20
target/riscv: rvv-1.0: remove widening saturating scaled multiply-add
Frank Chang
4
-243
/
+0
2021-12-20
target/riscv: rvv-1.0: single-width scaling shift instructions
Frank Chang
1
-2
/
+2
[next]