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AgeCommit message (Expand)AuthorFilesLines
2022-01-08target/riscv: Implement the stval/mtval illegal instructionAlistair Francis3-0/+8
2022-01-08target/riscv: Fixup setting GVAAlistair Francis1-15/+6
2022-01-08target/riscv: Set the opcode in DisasContextAlistair Francis1-0/+2
2022-01-08target/riscv: actual functions to realize crs 128-bit insnsFrédéric Pétrot3-30/+175
2022-01-08target/riscv: modification of the trans_csrxx for 128-bit supportFrédéric Pétrot1-43/+158
2022-01-08target/riscv: helper functions to wrap calls to 128-bit csr insnsFrédéric Pétrot4-0/+69
2022-01-08target/riscv: adding high part of some csrsFrédéric Pétrot2-0/+6
2022-01-08target/riscv: support for 128-bit M extensionFrédéric Pétrot6-13/+295
2022-01-08target/riscv: support for 128-bit arithmetic instructionsFrédéric Pétrot5-49/+222
2022-01-08target/riscv: support for 128-bit shift instructionsFrédéric Pétrot4-44/+270
2022-01-08target/riscv: support for 128-bit U-type instructionsFrédéric Pétrot2-4/+25
2022-01-08target/riscv: support for 128-bit bitwise instructionsFrédéric Pétrot1-2/+19
2022-01-08target/riscv: accessors to registers upper part and 128-bit load/storeFrédéric Pétrot4-10/+163
2022-01-08target/riscv: moving some insns close to similar insnsFrédéric Pétrot1-17/+17
2022-01-08target/riscv: setup everything for rv64 to support rv128 executionFrédéric Pétrot3-0/+26
2022-01-08target/riscv: array for the 64 upper bits of 128-bit registersFrédéric Pétrot4-1/+35
2022-01-08target/riscv: separation of bitwise logic and arithmetic helpersFrédéric Pétrot3-9/+36
2022-01-08target/riscv: additional macros to check instruction supportFrédéric Pétrot1-4/+16
2022-01-08exec/memop: Adding signedness to quad definitionsFrédéric Pétrot4-17/+17
2022-01-08target/riscv: Fix position of 'experimental' commentPhilipp Tomsich1-1/+2
2022-01-08target/riscv: rvv-1.0: Call the correct RVF/RVD check function for narrowing ...Frank Chang1-8/+24
2022-01-08target/riscv: rvv-1.0: Call the correct RVF/RVD check function for widening f...Frank Chang1-9/+25
2022-01-08target/riscv: rvv-1.0: Call the correct RVF/RVD check function for widening f...Frank Chang1-4/+8
2022-01-08target/riscv: Enable the Hypervisor extension by defaultAlistair Francis1-1/+1
2022-01-08target/riscv: Mark the Hypervisor extension as non experimentalAlistair Francis1-1/+1
2022-01-08target/riscv/pmp: fix no pmp illegal intrsNikita Shubin1-1/+2
2021-12-20target/riscv: Enable bitmanip Zb[abcs] instructionsVineet Gupta1-4/+4
2021-12-20target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructionsFrank Chang2-6/+13
2021-12-20target/riscv: rvv-1.0: update opivv_vadc_check() commentFrank Chang1-1/+1
2021-12-20target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmo...Frank Chang4-8/+8
2021-12-20target/riscv: rvv-1.0: add vector unit-stride mask load/store insnsFrank Chang4-0/+67
2021-12-20target/riscv: rvv-1.0: add evl parameter to vext_ldst_us()Frank Chang1-18/+18
2021-12-20target/riscv: rvv-1.0: add vsetivli instructionFrank Chang2-0/+29
2021-12-20target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11Frank Chang1-2/+2
2021-12-20target/riscv: rvv-1.0: floating-point reciprocal estimate instructionFrank Chang4-0/+197
2021-12-20target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruc...Frank Chang4-0/+189
2021-12-20target/riscv: gdb: support vector registers for rv64 & rv32Hsiangkai Wang3-0/+187
2021-12-20target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not validFrank Chang1-0/+22
2021-12-20target/riscv: rvv-1.0: implement vstart CSRFrank Chang5-103/+199
2021-12-20target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bitsFrank Chang3-4/+4
2021-12-20target/riscv: rvv-1.0: narrowing floating-point/integer type-convertFrank Chang4-44/+97
2021-12-20target/riscv: add "set round to odd" rounding mode helper functionFrank Chang4-0/+14
2021-12-20target/riscv: rvv-1.0: widening floating-point/integer type-convertFrank Chang4-14/+63
2021-12-20target/riscv: rvv-1.0: floating-point/integer type-convert instructionsFrank Chang2-36/+59
2021-12-20target/riscv: introduce floating-point rounding mode enumFrank Chang3-15/+24
2021-12-20target/riscv: rvv-1.0: floating-point min/max instructionsFrank Chang1-12/+12
2021-12-20target/riscv: rvv-1.0: remove integer extract instructionFrank Chang2-24/+0
2021-12-20target/riscv: rvv-1.0: remove vmford.vv and vmford.vfFrank Chang4-17/+0
2021-12-20target/riscv: rvv-1.0: remove widening saturating scaled multiply-addFrank Chang4-243/+0
2021-12-20target/riscv: rvv-1.0: single-width scaling shift instructionsFrank Chang1-2/+2
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