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| author | Frank Chang <frank.chang@sifive.com> | 2021-12-10 15:56:57 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2021-12-20 14:53:31 +1000 |
| commit | 6b5c8eb3e7de3c1b9dc2845b6b001ddd7d2eb359 (patch) | |
| tree | 5dbc4552c290d4f7db75a1846725bdd2a8d0fd5a /target/riscv | |
| parent | 55c35407c3706148761373aaa1d3350b57e86e8d (diff) | |
| download | qemu-6b5c8eb3e7de3c1b9dc2845b6b001ddd7d2eb359.zip qemu-6b5c8eb3e7de3c1b9dc2845b6b001ddd7d2eb359.tar.gz qemu-6b5c8eb3e7de3c1b9dc2845b6b001ddd7d2eb359.tar.bz2 | |
target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11
Rename r2_zimm to r2_zimm11 for the upcoming vsetivli instruction.
vsetivli has 10-bits of zimm but vsetvli has 11-bits of zimm.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-72-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv')
| -rw-r--r-- | target/riscv/insn32.decode | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 952768f..d7c6bc9 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -78,7 +78,7 @@ @r_vm ...... vm:1 ..... ..... ... ..... ....... &rmrr %rs2 %rs1 %rd @r_vm_1 ...... . ..... ..... ... ..... ....... &rmrr vm=1 %rs2 %rs1 %rd @r_vm_0 ...... . ..... ..... ... ..... ....... &rmrr vm=0 %rs2 %rs1 %rd -@r2_zimm . zimm:11 ..... ... ..... ....... %rs1 %rd +@r2_zimm11 . zimm:11 ..... ... ..... ....... %rs1 %rd @r2_s ....... ..... ..... ... ..... ....... %rs2 %rs1 @hfence_gvma ....... ..... ..... ... ..... ....... %rs2 %rs1 @@ -671,7 +671,7 @@ vsext_vf2 010010 . ..... 00111 010 ..... 1010111 @r2_vm vsext_vf4 010010 . ..... 00101 010 ..... 1010111 @r2_vm vsext_vf8 010010 . ..... 00011 010 ..... 1010111 @r2_vm -vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm +vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm11 vsetvl 1000000 ..... ..... 111 ..... 1010111 @r # *** RV32 Zba Standard Extension *** |