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Author
Files
Lines
2023-07-10
riscv: Add support for the Zfa extension
Christoph Müllner
1
-0
/
+521
2023-07-10
target/riscv: Add support for Zvfbfwma extension
Weiwei Li
1
-0
/
+58
2023-07-10
target/riscv: Add support for Zvfbfmin extension
Weiwei Li
1
-0
/
+64
2023-07-10
target/riscv: Add support for Zfbfmin extension
Weiwei Li
2
-6
/
+59
2023-06-13
target/riscv: Enable PC-relative translation
Weiwei Li
2
-3
/
+13
2023-06-13
target/riscv: Use true diff for gen_pc_plus_diff
Weiwei Li
2
-5
/
+3
2023-06-13
target/riscv: Change gen_set_pc_imm to gen_update_pc
Weiwei Li
5
-8
/
+8
2023-06-13
target/riscv: Change gen_goto_tb to work on displacements
Weiwei Li
1
-2
/
+2
2023-06-13
target/riscv: Fix target address to update badaddr
Weiwei Li
2
-9
/
+18
2023-06-13
target/riscv: Reuse tb->flags.FS
Mayuresh Chitale
1
-3
/
+4
2023-06-13
target/riscv: Update check for Zca/Zcf/Zcd
Weiwei Li
3
-13
/
+18
2023-06-05
accel/tcg: Introduce translator_io_start
Richard Henderson
2
-24
/
+8
2023-05-05
target/riscv: Handle HLV, HSV via helpers
Richard Henderson
1
-78
/
+51
2023-05-05
target/riscv: Reduce overhead of MSTATUS_SUM change
Fei Wu
1
-2
/
+2
2023-05-05
target/riscv: Separate priv from mmu_idx
Fei Wu
2
-14
/
+2
2023-05-05
target/riscv: Add a tb flags field for vstart
LIU Zhiwei
1
-7
/
+7
2023-05-05
target/riscv: Encode the FS and VS on a normal way for tb flags
LIU Zhiwei
2
-5
/
+5
2023-05-05
target/riscv: remove cpu->cfg.ext_e
Daniel Henrique Barboza
1
-1
/
+1
2023-05-05
target/riscv: Fix format for comments
Weiwei Li
1
-3
/
+5
2023-05-05
target/riscv: Fix format for indentation
Weiwei Li
1
-14
/
+14
2023-05-05
target/riscv: Set opcode to env->bins for illegal/virtual instruction fault
Weiwei Li
1
-0
/
+2
2023-05-05
target/riscv: Fix itrigger when icount is used
LIU Zhiwei
1
-0
/
+6
2023-05-05
target/riscv: add support for Zcmt extension
Weiwei Li
1
-1
/
+27
2023-05-05
target/riscv: add support for Zcmp extension
Weiwei Li
1
-1
/
+186
2023-05-05
target/riscv: add support for Zcb extension
Weiwei Li
1
-0
/
+100
2023-05-05
target/riscv: add support for Zcd extension
Weiwei Li
1
-0
/
+18
2023-05-05
target/riscv: add support for Zcf extension
Weiwei Li
1
-0
/
+18
2023-05-05
target/riscv: add support for Zca extension
Weiwei Li
1
-2
/
+2
2023-05-05
target/riscv: redirect XVentanaCondOps to use the Zicond functions
Philipp Tomsich
1
-15
/
+3
2023-05-05
target/riscv: refactor Zicond support
Philipp Tomsich
1
-15
/
+21
2023-03-07
Merge tag 'pull-riscv-to-apply-20230306' of https://gitlab.com/palmer-dabbelt...
Peter Maydell
1
-0
/
+57
2023-03-05
target/riscv: Avoid tcg_const_*
Richard Henderson
2
-3
/
+3
2023-03-05
target/riscv: Drop tcg_temp_free
Richard Henderson
9
-208
/
+1
2023-03-05
target/riscv: Drop temp_new
Richard Henderson
1
-1
/
+1
2023-03-05
target/riscv: implement Zicbom extension
Christoph Muellner
1
-0
/
+27
2023-03-05
target/riscv: implement Zicboz extension
Christoph Muellner
1
-0
/
+30
2023-03-01
target/riscv: Add support for Zicond extension
Weiwei Li
1
-0
/
+49
2023-03-01
RISC-V: XTheadMemPair: Remove register restrictions for store-pair
Christoph Müllner
1
-4
/
+0
2023-03-01
target/riscv: Simplify check for EEW = 64 in trans_rvv.c.inc
Weiwei Li
1
-8
/
+4
2023-03-01
target/riscv: Fix check for vector load/store instructions when EEW=64
Weiwei Li
1
-5
/
+4
2023-03-01
target/riscv: Add support for Zvfh/zvfhmin extensions
Weiwei Li
1
-2
/
+29
2023-03-01
target/riscv: Remove redundunt check for zve32f and zve64f
Weiwei Li
1
-107
/
+21
2023-03-01
target/riscv: Replace check for F/D to Zve32f/Zve64d in trans_rvv.c.inc
Weiwei Li
1
-4
/
+4
2023-03-01
target/riscv: Simplify check for Zve32f and Zve64f
Weiwei Li
1
-6
/
+2
2023-03-01
target/riscv: Simplify the check for Zfhmin and Zhinxmin
Weiwei Li
1
-13
/
+12
2023-02-07
target/riscv: fix ctzw behavior
Vladimir Isaev
1
-0
/
+1
2023-02-07
RISC-V: Adding XTheadFmv ISA extension
Christoph Müllner
1
-0
/
+45
2023-02-07
RISC-V: Adding T-Head FMemIdx extension
Christoph Müllner
1
-0
/
+108
2023-02-07
RISC-V: Adding T-Head MemIdx extension
Christoph Müllner
1
-0
/
+387
2023-02-07
RISC-V: Adding T-Head MemPair extension
Christoph Müllner
1
-0
/
+92
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