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AgeCommit message (Expand)AuthorFilesLines
2022-05-24target/riscv: rvv: Fix early exit condition for whole register load/storeeopXD1-27/+31
2022-04-29target/riscv: rvk: add support for zksed/zksh extensionWeiwei Li1-0/+58
2022-04-29target/riscv: rvk: add support for sha512 related instructions for RV64 in zk...Weiwei Li1-0/+53
2022-04-29target/riscv: rvk: add support for sha512 related instructions for RV32 in zk...Weiwei Li1-0/+100
2022-04-29target/riscv: rvk: add support for sha256 related instructions in zknh extensionWeiwei Li1-0/+55
2022-04-29target/riscv: rvk: add support for zkne/zknd extension in RV64Weiwei Li1-0/+54
2022-04-29target/riscv: rvk: add support for zknd/zkne extension in RV32Weiwei Li1-0/+71
2022-04-29target/riscv: rvk: add support for zbkx extensionWeiwei Li1-0/+18
2022-04-29target/riscv: rvk: add support for zbkc extensionWeiwei Li1-2/+2
2022-04-29target/riscv: rvk: add support for zbkb extensionWeiwei Li1-12/+82
2022-04-22target/riscv: optimize helper for vmv<nr>r.vWeiwei Li1-11/+6
2022-04-22target/riscv: optimize condition assign for scale < 0Weiwei Li1-5/+3
2022-04-06Replace config-time define HOST_WORDS_BIGENDIANMarc-André Lureau1-2/+2
2022-04-01target/riscv: rvv: Add missing early exit condition for whole register load/s...Yueh-Ting (eop) Chen1-0/+5
2022-03-03target/riscv: add support for zhinx/zhinxminWeiwei Li1-95/+237
2022-03-03target/riscv: add support for zdinxWeiwei Li1-78/+207
2022-03-03target/riscv: add support for zfinxWeiwei Li1-96/+218
2022-03-03target/riscv: fix inverted checks for ext_zb[abcs]Philipp Tomsich1-4/+4
2022-02-16target/riscv: add support for svinval extensionWeiwei Li1-0/+75
2022-02-16target/riscv: Add XVentanaCondOps custom extensionPhilipp Tomsich1-0/+39
2022-02-16target/riscv: access cfg structure through DisasContextPhilipp Tomsich1-4/+4
2022-02-16target/riscv: access configuration through cfg_ptr in DisasContextPhilipp Tomsich3-55/+97
2022-01-21target/riscv: Adjust scalar reg in vector with XLENLIU Zhiwei1-1/+1
2022-01-21target/riscv: Calculate address according to XLENLIU Zhiwei4-56/+9
2022-01-21target/riscv: Adjust csr write mask with XLENLIU Zhiwei1-4/+8
2022-01-21target/riscv: Sign extend pc for different XLENLIU Zhiwei3-5/+6
2022-01-21target/riscv: Sign extend link reg for jal and jalrLIU Zhiwei1-3/+1
2022-01-21target/riscv: Don't save pc when exception returnLIU Zhiwei1-5/+2
2022-01-21target/riscv: rvv-1.0: Add Zve32f support for narrowing type-convert insnsFrank Chang1-0/+3
2022-01-21target/riscv: rvv-1.0: Add Zve32f support for widening type-convert insnsFrank Chang1-0/+18
2022-01-21target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insnsFrank Chang1-0/+1
2022-01-21target/riscv: rvv-1.0: Add Zve32f support for scalar fp insnsFrank Chang1-0/+21
2022-01-21target/riscv: rvv-1.0: Add Zve32f support for configuration insnsFrank Chang1-2/+2
2022-01-21target/riscv: rvv-1.0: Add Zve64f support for narrowing type-convert insnsFrank Chang1-3/+6
2022-01-21target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insnsFrank Chang1-7/+25
2022-01-21target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insnsFrank Chang1-1/+2
2022-01-21target/riscv: rvv-1.0: Add Zve64f support for scalar fp insnsFrank Chang1-10/+31
2022-01-21target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insnsFrank Chang1-2/+25
2022-01-21target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insnsFrank Chang1-6/+33
2022-01-21target/riscv: rvv-1.0: Add Zve64f support for load and store insnsFrank Chang1-4/+15
2022-01-21target/riscv: rvv-1.0: Add Zve64f support for configuration insnsFrank Chang1-2/+4
2022-01-08target/riscv: modification of the trans_csrxx for 128-bit supportFrédéric Pétrot1-43/+158
2022-01-08target/riscv: support for 128-bit M extensionFrédéric Pétrot1-13/+169
2022-01-08target/riscv: support for 128-bit arithmetic instructionsFrédéric Pétrot3-37/+168
2022-01-08target/riscv: support for 128-bit shift instructionsFrédéric Pétrot2-29/+217
2022-01-08target/riscv: support for 128-bit U-type instructionsFrédéric Pétrot1-4/+4
2022-01-08target/riscv: accessors to registers upper part and 128-bit load/storeFrédéric Pétrot1-6/+94
2022-01-08target/riscv: moving some insns close to similar insnsFrédéric Pétrot1-17/+17
2022-01-08target/riscv: separation of bitwise logic and arithmetic helpersFrédéric Pétrot2-9/+9
2022-01-08exec/memop: Adding signedness to quad definitionsFrédéric Pétrot4-17/+17
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