diff options
| author | Frank Chang <frank.chang@sifive.com> | 2022-01-18 09:45:17 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-01-21 15:52:56 +1000 |
| commit | 8527b5db728b572c288fdcadb126d369040731be (patch) | |
| tree | a36234993641d5448acc7964448ab3ae7de7e5a8 /target/riscv/insn_trans | |
| parent | abe2d74032d6d12a6918715086bbdf8843296f36 (diff) | |
| download | qemu-8527b5db728b572c288fdcadb126d369040731be.zip qemu-8527b5db728b572c288fdcadb126d369040731be.tar.gz qemu-8527b5db728b572c288fdcadb126d369040731be.tar.bz2 | |
target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insns
Vector single-width floating-point reduction operations for EEW=32 are
supported for Zve32f extension.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-15-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/insn_trans')
| -rw-r--r-- | target/riscv/insn_trans/trans_rvv.c.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index fe4ad5d..b02bb55 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2976,6 +2976,7 @@ static bool freduction_check(DisasContext *s, arg_rmrr *a) { return reduction_check(s, a) && require_rvf(s) && + require_zve32f(s) && require_zve64f(s); } |