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2024-01-10target/riscv: Add support for Zacas extensionWeiwei Li1-0/+150
2024-01-10target/riscv: Fix th.dcache.cval1 priviledge checkLIU Zhiwei1-1/+1
2024-01-10target/riscv: The whole vector register move instructions depend on vsewMax Chou1-2/+1
2024-01-10target/riscv: Add vill check for whole vector register move instructionsMax Chou1-2/+3
2023-11-07target/riscv: Replace Zvbb checking by ZvkbMax Chou1-13/+24
2023-11-07target/riscv: rename ext_icboz to ext_zicbozDaniel Henrique Barboza1-4/+4
2023-11-07target/riscv: rename ext_icbom to ext_zicbomDaniel Henrique Barboza1-4/+4
2023-11-07target/riscv: rename ext_ifencei to ext_zifenceiDaniel Henrique Barboza1-1/+1
2023-10-03tcg: Rename cpu_env to tcg_envRichard Henderson15-211/+211
2023-09-11target/riscv: Fix zfa fleq.d and fltq.dLIU Zhiwei1-2/+2
2023-09-11target/riscv: Add Zvksed ISA extension supportMax Chou1-0/+43
2023-09-11target/riscv: Add Zvkg ISA extension supportNazar Kazakov1-0/+30
2023-09-11target/riscv: Add Zvksh ISA extension supportLawrence Hunter1-0/+31
2023-09-11target/riscv: Add Zvknh ISA extension supportKiran Ostrolenk1-0/+129
2023-09-11target/riscv: Add Zvkned ISA extension supportNazar Kazakov1-0/+147
2023-09-11target/riscv: Add Zvbb ISA extension supportDickon Hood1-0/+164
2023-09-11target/riscv: Refactor translation of vector-widening instructionDickon Hood1-29/+23
2023-09-11target/riscv: Move vector translation checksNazar Kazakov1-16/+12
2023-09-11target/riscv: Add Zvbc ISA extension supportLawrence Hunter1-0/+62
2023-09-11target/riscv: Remove redundant "cpu_vl == 0" checksNazar Kazakov1-30/+1
2023-09-11target/riscv: Refactor vector-vector translation macroKiran Ostrolenk1-30/+32
2023-09-08riscv: spelling fixesMichael Tokarev3-6/+6
2023-07-10riscv: Add support for the Zfa extensionChristoph Müllner1-0/+521
2023-07-10target/riscv: Add support for Zvfbfwma extensionWeiwei Li1-0/+58
2023-07-10target/riscv: Add support for Zvfbfmin extensionWeiwei Li1-0/+64
2023-07-10target/riscv: Add support for Zfbfmin extensionWeiwei Li2-6/+59
2023-06-13target/riscv: Enable PC-relative translationWeiwei Li2-3/+13
2023-06-13target/riscv: Use true diff for gen_pc_plus_diffWeiwei Li2-5/+3
2023-06-13target/riscv: Change gen_set_pc_imm to gen_update_pcWeiwei Li5-8/+8
2023-06-13target/riscv: Change gen_goto_tb to work on displacementsWeiwei Li1-2/+2
2023-06-13target/riscv: Fix target address to update badaddrWeiwei Li2-9/+18
2023-06-13target/riscv: Reuse tb->flags.FSMayuresh Chitale1-3/+4
2023-06-13target/riscv: Update check for Zca/Zcf/ZcdWeiwei Li3-13/+18
2023-06-05accel/tcg: Introduce translator_io_startRichard Henderson2-24/+8
2023-05-05target/riscv: Handle HLV, HSV via helpersRichard Henderson1-78/+51
2023-05-05target/riscv: Reduce overhead of MSTATUS_SUM changeFei Wu1-2/+2
2023-05-05target/riscv: Separate priv from mmu_idxFei Wu2-14/+2
2023-05-05target/riscv: Add a tb flags field for vstartLIU Zhiwei1-7/+7
2023-05-05target/riscv: Encode the FS and VS on a normal way for tb flagsLIU Zhiwei2-5/+5
2023-05-05target/riscv: remove cpu->cfg.ext_eDaniel Henrique Barboza1-1/+1
2023-05-05target/riscv: Fix format for commentsWeiwei Li1-3/+5
2023-05-05target/riscv: Fix format for indentationWeiwei Li1-14/+14
2023-05-05target/riscv: Set opcode to env->bins for illegal/virtual instruction faultWeiwei Li1-0/+2
2023-05-05target/riscv: Fix itrigger when icount is usedLIU Zhiwei1-0/+6
2023-05-05target/riscv: add support for Zcmt extensionWeiwei Li1-1/+27
2023-05-05target/riscv: add support for Zcmp extensionWeiwei Li1-1/+186
2023-05-05target/riscv: add support for Zcb extensionWeiwei Li1-0/+100
2023-05-05target/riscv: add support for Zcd extensionWeiwei Li1-0/+18
2023-05-05target/riscv: add support for Zcf extensionWeiwei Li1-0/+18
2023-05-05target/riscv: add support for Zca extensionWeiwei Li1-2/+2
generated by cgit v1.1 at 2024-11-03 11:10:26 +0000