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2023-03-07Merge tag 'pull-riscv-to-apply-20230306' of https://gitlab.com/palmer-dabbelt...Peter Maydell1-0/+57
2023-03-05target/riscv: Avoid tcg_const_*Richard Henderson2-3/+3
2023-03-05target/riscv: Drop tcg_temp_freeRichard Henderson9-208/+1
2023-03-05target/riscv: Drop temp_newRichard Henderson1-1/+1
2023-03-05target/riscv: implement Zicbom extensionChristoph Muellner1-0/+27
2023-03-05target/riscv: implement Zicboz extensionChristoph Muellner1-0/+30
2023-03-01target/riscv: Add support for Zicond extensionWeiwei Li1-0/+49
2023-03-01RISC-V: XTheadMemPair: Remove register restrictions for store-pairChristoph Müllner1-4/+0
2023-03-01target/riscv: Simplify check for EEW = 64 in trans_rvv.c.incWeiwei Li1-8/+4
2023-03-01target/riscv: Fix check for vector load/store instructions when EEW=64Weiwei Li1-5/+4
2023-03-01target/riscv: Add support for Zvfh/zvfhmin extensionsWeiwei Li1-2/+29
2023-03-01target/riscv: Remove redundunt check for zve32f and zve64fWeiwei Li1-107/+21
2023-03-01target/riscv: Replace check for F/D to Zve32f/Zve64d in trans_rvv.c.incWeiwei Li1-4/+4
2023-03-01target/riscv: Simplify check for Zve32f and Zve64fWeiwei Li1-6/+2
2023-03-01target/riscv: Simplify the check for Zfhmin and ZhinxminWeiwei Li1-13/+12
2023-02-07target/riscv: fix ctzw behaviorVladimir Isaev1-0/+1
2023-02-07RISC-V: Adding XTheadFmv ISA extensionChristoph Müllner1-0/+45
2023-02-07RISC-V: Adding T-Head FMemIdx extensionChristoph Müllner1-0/+108
2023-02-07RISC-V: Adding T-Head MemIdx extensionChristoph Müllner1-0/+387
2023-02-07RISC-V: Adding T-Head MemPair extensionChristoph Müllner1-0/+92
2023-02-07RISC-V: Adding T-Head multiply-accumulate instructionsChristoph Müllner1-0/+83
2023-02-07RISC-V: Adding XTheadCondMov ISA extensionChristoph Müllner1-0/+35
2023-02-07RISC-V: Adding XTheadBs ISA extensionChristoph Müllner1-0/+15
2023-02-07RISC-V: Adding XTheadBb ISA extensionChristoph Müllner1-0/+124
2023-02-07RISC-V: Adding XTheadBa ISA extensionChristoph Müllner1-0/+39
2023-02-07RISC-V: Adding XTheadSync ISA extensionChristoph Müllner1-0/+85
2023-02-07RISC-V: Adding XTheadCmo ISA extensionChristoph Müllner1-0/+81
2023-02-07target/riscv: Ensure opcode is saved for all relevant instructionsAnup Patel7-3/+21
2023-01-20target/riscv: Introduce helper_set_rounding_mode_chkfrmRichard Henderson1-20/+4
2023-01-06RISC-V: Add Zawrs ISA extension supportChristoph Muellner1-0/+51
2023-01-06target/riscv: Add itrigger support when icount is not enabledLIU Zhiwei3-8/+8
2022-09-27target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unorderedYang Liu1-2/+4
2022-09-13target/riscv: Honour -semihosting-config userspace=on and enable=onPeter Maydell1-1/+2
2022-09-07target/riscv: Add Zihintpause supportDao Lu1-0/+16
2022-09-07target/riscv: rvv: Add mask agnostic for vector permutation instructionsYueh-Ting (eop) Chen1-0/+1
2022-09-07target/riscv: rvv: Add mask agnostic for vector mask instructionsYueh-Ting (eop) Chen1-0/+3
2022-09-07target/riscv: rvv: Add mask agnostic for vector floating-point instructionsYueh-Ting (eop) Chen1-0/+12
2022-09-07target/riscv: rvv: Add mask agnostic for vector integer comparison instructionsYueh-Ting (eop) Chen1-0/+1
2022-09-07target/riscv: rvv: Add mask agnostic for vector integer shift instructionsYueh-Ting (eop) Chen1-0/+1
2022-09-07target/riscv: rvv: Add mask agnostic for vx instructionsYueh-Ting (eop) Chen1-0/+2
2022-09-07target/riscv: rvv: Add mask agnostic for vector load / store instructionsYueh-Ting (eop) Chen1-0/+5
2022-09-07target/riscv: rvv: Add mask agnostic for vv instructionsYueh-Ting (eop) Chen1-0/+3
2022-07-03target/riscv: Minimize the calls to decode_save_opcRichard Henderson3-0/+8
2022-07-03target/riscv: Remove condition guarding register zero for auipc and luiVíctor Colombo1-6/+2
2022-06-10target/riscv: trans_rvv: Avoid assert for RV32 and e64Alistair Francis1-2/+10
2022-06-10target/riscv: rvv: Add tail agnostic for vector permutation instructionseopXD1-2/+5
2022-06-10target/riscv: rvv: Add tail agnostic for vector mask instructionseopXD1-0/+6
2022-06-10target/riscv: rvv: Add tail agnostic for vector floating-point instructionseopXD1-0/+17
2022-06-10target/riscv: rvv: Add tail agnostic for vector integer merge and move instru...eopXD1-4/+8
2022-06-10target/riscv: rvv: Add tail agnostic for vector integer shift instructionseopXD1-1/+2
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