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path: root/target/riscv/insn_trans/trans_rvi.c.inc
AgeCommit message (Expand)AuthorFilesLines
2024-08-06target/riscv: Remove redundant insn length check for zama16bLIU Zhiwei1-2/+2
2024-07-18target/riscv: Support Zama16b extensionLIU Zhiwei1-0/+6
2024-03-08RISC-V: Add support for ZtsoPalmer Dabbelt1-2/+14
2023-11-07target/riscv: rename ext_ifencei to ext_zifenceiDaniel Henrique Barboza1-1/+1
2023-10-03tcg: Rename cpu_env to tcg_envRichard Henderson1-8/+8
2023-06-13target/riscv: Enable PC-relative translationWeiwei Li1-2/+10
2023-06-13target/riscv: Use true diff for gen_pc_plus_diffWeiwei Li1-4/+2
2023-06-13target/riscv: Change gen_set_pc_imm to gen_update_pcWeiwei Li1-3/+3
2023-06-13target/riscv: Change gen_goto_tb to work on displacementsWeiwei Li1-2/+2
2023-06-13target/riscv: Fix target address to update badaddrWeiwei Li1-7/+16
2023-06-13target/riscv: Update check for Zca/Zcf/ZcdWeiwei Li1-2/+3
2023-06-05accel/tcg: Introduce translator_io_startRichard Henderson1-18/+6
2023-05-05target/riscv: add support for Zca extensionWeiwei Li1-2/+2
2023-03-05target/riscv: Drop tcg_temp_freeRichard Henderson1-37/+0
2023-02-07target/riscv: Ensure opcode is saved for all relevant instructionsAnup Patel1-0/+2
2023-01-06target/riscv: Add itrigger support when icount is not enabledLIU Zhiwei1-4/+4
2022-09-07target/riscv: Add Zihintpause supportDao Lu1-0/+16
2022-07-03target/riscv: Minimize the calls to decode_save_opcRichard Henderson1-0/+2
2022-07-03target/riscv: Remove condition guarding register zero for auipc and luiVíctor Colombo1-6/+2
2022-02-16target/riscv: access configuration through cfg_ptr in DisasContextPhilipp Tomsich1-1/+1
2022-01-21target/riscv: Calculate address according to XLENLIU Zhiwei1-16/+2
2022-01-21target/riscv: Adjust csr write mask with XLENLIU Zhiwei1-4/+8
2022-01-21target/riscv: Sign extend pc for different XLENLIU Zhiwei1-2/+3
2022-01-21target/riscv: Sign extend link reg for jal and jalrLIU Zhiwei1-3/+1
2022-01-08target/riscv: modification of the trans_csrxx for 128-bit supportFrédéric Pétrot1-43/+158
2022-01-08target/riscv: support for 128-bit arithmetic instructionsFrédéric Pétrot1-14/+145
2022-01-08target/riscv: support for 128-bit shift instructionsFrédéric Pétrot1-18/+206
2022-01-08target/riscv: support for 128-bit U-type instructionsFrédéric Pétrot1-4/+4
2022-01-08target/riscv: accessors to registers upper part and 128-bit load/storeFrédéric Pétrot1-6/+94
2022-01-08target/riscv: moving some insns close to similar insnsFrédéric Pétrot1-17/+17
2022-01-08target/riscv: separation of bitwise logic and arithmetic helpersFrédéric Pétrot1-6/+6
2022-01-08exec/memop: Adding signedness to quad definitionsFrédéric Pétrot1-2/+2
2021-10-28target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instr...Alexey Baturo1-0/+2
2021-10-22target/riscv: Use gen_shift*_per_ol for RVB, RVIRichard Henderson1-12/+14
2021-10-22target/riscv: Replace DisasContext.w with DisasContext.olRichard Henderson1-9/+9
2021-10-15target/riscv: Remove exit_tb and lookup_and_goto_ptrRichard Henderson1-5/+3
2021-09-01target/riscv: Reorg csr instructionsRichard Henderson1-52/+122
2021-09-01target/riscv: Use {get, dest}_gpr for integer load/storeRichard Henderson1-18/+20
2021-09-01target/riscv: Use get_gpr in branchesRichard Henderson1-15/+10
2021-09-01target/riscv: Use extracts for sraiw and srliwRichard Henderson1-2/+12
2021-09-01target/riscv: Use DisasExtend in shift operationsRichard Henderson1-70/+18
2021-09-01target/riscv: Add DisasExtend to gen_arith*Richard Henderson1-17/+22
2021-09-01target/riscv: Add DisasContext to gen_get_gpr, gen_set_gprRichard Henderson1-22/+22
2021-06-08target/riscv: add gen_shifti() and gen_shiftiw() helper functionsFrank Chang1-50/+4
2021-05-11target/riscv: Consolidate RV32/64 16-bit instructionsAlistair Francis1-0/+6
2021-05-11target/riscv: Consolidate RV32/64 32-bit instructionsAlistair Francis1-4/+12
2020-08-21meson: rename included C source files to .c.incPaolo Bonzini1-0/+577
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