riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
4 days	target/riscv: update `decode_save_opc` to store extra word2	Deepak Gupta	1	-4/+4
2023-10-03	tcg: Rename cpu_env to tcg_env	Richard Henderson	1	-4/+4
2023-05-05	target/riscv: Handle HLV, HSV via helpers	Richard Henderson	1	-78/+51
2023-05-05	target/riscv: Reduce overhead of MSTATUS_SUM change	Fei Wu	1	-2/+2
2023-05-05	target/riscv: Set opcode to env->bins for illegal/virtual instruction fault	Weiwei Li	1	-0/+2
2023-02-07	target/riscv: Ensure opcode is saved for all relevant instructions	Anup Patel	1	-0/+3
2022-07-03	target/riscv: Minimize the calls to decode_save_opc	Richard Henderson	1	-0/+2
2022-01-08	exec/memop: Adding signedness to quad definitions	Frédéric Pétrot	1	-2/+2
2021-09-01	target/riscv: Tidy trans_rvh.c.inc	Richard Henderson	1	-210/+56
2021-09-01	target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr	Richard Henderson	1	-26/+26
2021-05-11	target/riscv: Consolidate RV32/64 32-bit instructions	Alistair Francis	1	-2/+6
2020-11-09	target/riscv: Split the Hypervisor execute load helpers	Alistair Francis	1	-14/+6
2020-11-09	target/riscv: Remove the hyp load and store functions	Alistair Francis	1	-78/+45
2020-08-25	target/riscv: Support the Virtual Instruction fault	Alistair Francis	1	-1/+1
2020-08-25	target/riscv: Allow generating hlv/hlvx/hsv instructions	Alistair Francis	1	-0/+340
2020-08-21	meson: rename included C source files to .c.inc	Paolo Bonzini	1	-0/+37