riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2024-06-03	trans_privileged.c.inc: set (m\|s)tval on ebreak breakpoint	Daniel Henrique Barboza	1	-0/+2
2023-10-03	tcg: Rename cpu_env to tcg_env	Richard Henderson	1	-4/+4
2023-06-13	target/riscv: Change gen_set_pc_imm to gen_update_pc	Weiwei Li	1	-1/+1
2023-06-05	accel/tcg: Introduce translator_io_start	Richard Henderson	1	-6/+2
2023-05-05	target/riscv: Separate priv from mmu_idx	Fei Wu	1	-1/+1
2023-05-05	target/riscv: Fix itrigger when icount is used	LIU Zhiwei	1	-0/+6
2023-01-06	target/riscv: Add itrigger support when icount is not enabled	LIU Zhiwei	1	-2/+2
2022-09-13	target/riscv: Honour -semihosting-config userspace=on and enable=on	Peter Maydell	1	-1/+2
2022-07-03	target/riscv: Minimize the calls to decode_save_opc	Richard Henderson	1	-0/+4
2022-01-21	target/riscv: Sign extend pc for different XLEN	LIU Zhiwei	1	-1/+1
2022-01-21	target/riscv: Don't save pc when exception return	LIU Zhiwei	1	-5/+2
2021-10-15	target/riscv: Remove exit_tb and lookup_and_goto_ptr	Richard Henderson	1	-2/+2
2021-10-15	target/riscv: Remove dead code after exception	Richard Henderson	1	-5/+1
2021-01-18	riscv: Add semihosting support	Keith Packard	1	-1/+36
2020-08-21	meson: rename included C source files to .c.inc	Paolo Bonzini	1	-0/+97