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path: root/target/riscv/cpu.h
AgeCommit message (Expand)AuthorFilesLines
2020-11-03target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unitYifei Jiang1-13/+11
2020-10-22target/riscv: raise exception to HS-mode at get_physical_addressYifei Jiang1-3/+7
2020-09-18qom: Remove module_obj_name parameter from OBJECT_DECLARE* macrosEduardo Habkost1-1/+1
2020-09-13Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20200...Peter Maydell1-2/+6
2020-09-09hw/riscv: clint: Avoid using hard-coded timebase frequencyBin Meng1-2/+4
2020-09-09target/riscv: cpu: Add a new 'resetvec' propertyBin Meng1-0/+1
2020-09-09target/riscv: Fix bug in getting trap cause name for trace_riscv_trapYifei Jiang1-0/+1
2020-09-09Use OBJECT_DECLARE_TYPE where possibleEduardo Habkost1-4/+2
2020-09-09Use DECLARE_*CHECKER* macrosEduardo Habkost1-6/+2
2020-09-09Move QOM typedefs and add missing includesEduardo Habkost1-4/+7
2020-08-25target/riscv: Allow setting a two-stage lookup in the virt statusAlistair Francis1-0/+2
2020-07-13target/riscv: fix vill bit index in vtype registerFrank Chang1-1/+1
2020-07-02target/riscv: configure and turn on vector extension from command lineLIU Zhiwei1-1/+3
2020-07-02target/riscv: add vector configure instructionLIU Zhiwei1-9/+54
2020-07-02target/riscv: implementation-defined constant parametersLIU Zhiwei1-0/+5
2020-07-02target/riscv: add vector extension field in CPURISCVStateLIU Zhiwei1-0/+12
2020-06-03target/riscv: Add the lowRISC Ibex CPUAlistair Francis1-0/+1
2020-06-03target/riscv: Drop support for ISA spec version 1.09.1Alistair Francis1-1/+0
2020-06-03target/riscv: Remove the deprecated CPUsAlistair Francis1-7/+0
2020-04-29target/riscv: Add a sifive-e34 cpu typeCorey Wharton1-0/+1
2020-03-19Merge remote-tracking branch 'remotes/ehabkost/tags/x86-and-machine-pull-requ...Peter Maydell1-1/+1
2020-03-17cpu: Use DeviceClass reset instead of a special CPUClass resetPeter Maydell1-1/+1
2020-03-17gdbstub: extend GByteArray to read register helpersAlex Bennée1-1/+1
2020-02-27target/riscv: Emulate TIME CSRs for privileged modeAnup Patel1-0/+5
2020-02-27target/riscv: Allow enabling the Hypervisor extensionAlistair Francis1-0/+1
2020-02-27target/riscv: Add support for the 32-bit MSTATUSH CSRAlistair Francis1-0/+10
2020-02-27target/riscv: Implement second stage MMUAlistair Francis1-0/+1
2020-02-27target/riscv: Only set TB flags with FP status if enabledAlistair Francis1-1/+4
2020-02-27target/riscv: Add virtual register swapping functionAlistair Francis1-0/+11
2020-02-27target/riscv: Add the force HS exception modeAlistair Francis1-0/+2
2020-02-27target/riscv: Add the virtulisation modeAlistair Francis1-0/+4
2020-02-27target/riscv: Add the Hypervisor CSRs to CPUStateAlistair Francis1-0/+21
2020-02-27target/riscv: Add the Hypervisor extensionAlistair Francis1-0/+1
2020-02-27target/riscv: Convert MIP CSR to target_ulongAlistair Francis1-1/+1
2020-01-16target/riscv: Fix tb->flags FS statusShihPo Hung1-4/+1
2019-11-14target/riscv: Remove atomic accesses to MIP CSRAlistair Francis1-9/+0
2019-10-28RISC-V: Implement cpu_do_transaction_failedPalmer Dabbelt1-2/+5
2019-09-17target/riscv: Use TB_FLAGS_MSTATUS_FS for floating pointAlistair Francis1-1/+1
2019-09-17target/riscv: Create function to test if FP is enabledAlistair Francis1-1/+5
2019-08-21hw/core: Move cpu.c, cpu.h from qom/ to hw/core/Markus Armbruster1-1/+1
2019-08-19target/riscv: rationalise softfloat includesAlex Bennée1-1/+1
2019-06-25RISC-V: Add support for the Zicsr extensionPalmer Dabbelt1-0/+1
2019-06-25RISC-V: Add support for the Zifencei extensionPalmer Dabbelt1-0/+1
2019-06-25target/riscv: Add support for disabling/enabling CountersAlistair Francis1-0/+1
2019-06-25target/riscv: Remove user version informationAlistair Francis1-2/+0
2019-06-24target/riscv: Add the privledge spec version 1.11.0Alistair Francis1-0/+1
2019-06-24target/riscv: Restructure deprecatd CPUsAlistair Francis1-6/+7
2019-06-23RISC-V: Check PMP during Page Table WalksHesham Almatary1-0/+1
2019-06-23target/riscv: Implement riscv_cpu_unassigned_accessMichael Clark1-0/+2
2019-06-23target/riscv: Allow setting ISA extensions via CPU propsAlistair Francis1-0/+11
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