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path: root/target/riscv/cpu.c
AgeCommit message (Expand)AuthorFilesLines
2024-04-25hw, target: Add ResetType argument to hold and exit phase methodsPeter Maydell1-2/+2
2024-03-22target/riscv: do not enable all named features by defaultDaniel Henrique Barboza1-31/+9
2024-03-12target: Replace CPU_GET_CLASS(cpu -> obj) in cpu_reset_hold() handlerPhilippe Mathieu-Daudé1-1/+1
2024-03-08target/riscv: move ratified/frozen exts to non-experimentalDaniel Henrique Barboza1-13/+9
2024-03-08RISC-V: Add support for ZtsoPalmer Dabbelt1-0/+2
2024-03-08target/riscv: Promote svade to a normal extensionAndrew Jones1-7/+2
2024-03-08target/riscv: Gate hardware A/D PTE bit updatingAndrew Jones1-1/+2
2024-03-08target/riscv: Reset henvcfg to zeroAndrew Jones1-2/+1
2024-03-08target/riscv: add remaining named featuresDaniel Henrique Barboza1-7/+35
2024-03-08target/riscv: add riscv,isa to named featuresDaniel Henrique Barboza1-4/+13
2024-02-28hw/core/cpu: Remove gdb_get_dynamic_xml memberAkihiko Odaki1-14/+0
2024-02-28gdbstub: Infer number of core registers from XMLAkihiko Odaki1-1/+0
2024-02-28target/riscv: Use GDBFeature for dynamic XMLAkihiko Odaki1-2/+2
2024-02-09target/riscv: add rv32i, rv32e and rv64e CPUsDaniel Henrique Barboza1-0/+21
2024-02-09target/riscv/cpu.c: add riscv_bare_cpu_init()Daniel Henrique Barboza1-16/+29
2024-02-09target/riscv: support new isa extension detection devicetree propertiesConor Dooley1-0/+54
2024-02-09target/riscv: use misa_mxl_max to populate isa string rather than TARGET_LONG...Conor Dooley1-1/+9
2024-02-09target/riscv: Expose Zaamo and Zalrsc extensionsRob Bradford1-0/+5
2024-02-09target/riscv: Validate misa_mxl_max only onceAkihiko Odaki1-0/+21
2024-02-09target/riscv: Move misa_mxl_max to classAkihiko Odaki1-76/+84
2024-02-09target/riscv/cpu.c: remove cpu->cfg.vlenDaniel Henrique Barboza1-5/+3
2024-02-09target/riscv: add 'vlenb' field in cpu->cfgDaniel Henrique Barboza1-1/+3
2024-02-09target/riscv/cpu.c: move 'marchid' to riscv_cpu_properties[]Daniel Henrique Barboza1-53/+57
2024-02-09target/riscv/cpu.c: move 'mimpid' to riscv_cpu_properties[]Daniel Henrique Barboza1-32/+36
2024-02-09target/riscv/cpu.c: move 'mvendorid' to riscv_cpu_properties[]Daniel Henrique Barboza1-32/+37
2024-02-09target/riscv: remove riscv_cpu_options[]Daniel Henrique Barboza1-5/+0
2024-02-09target/riscv: move 'cboz_blocksize' to riscv_cpu_properties[]Daniel Henrique Barboza1-1/+37
2024-02-09target/riscv: move 'cbop_blocksize' to riscv_cpu_properties[]Daniel Henrique Barboza1-1/+37
2024-02-09target/riscv: move 'cbom_blocksize' to riscv_cpu_properties[]Daniel Henrique Barboza1-1/+38
2024-02-09target/riscv: create finalize_features() for KVMDaniel Henrique Barboza1-5/+11
2024-02-09target/riscv: move 'elen' to riscv_cpu_properties[]Daniel Henrique Barboza1-2/+42
2024-02-09target/riscv: move 'vlen' to riscv_cpu_properties[]Daniel Henrique Barboza1-1/+44
2024-02-09target/riscv: rework 'vext_spec'Daniel Henrique Barboza1-2/+33
2024-02-09target/riscv: rework 'priv_spec'Daniel Henrique Barboza1-1/+72
2024-02-09target/riscv: move 'pmp' to riscv_cpu_properties[]Daniel Henrique Barboza1-2/+36
2024-02-09target/riscv: move 'mmu' to riscv_cpu_properties[]Daniel Henrique Barboza1-4/+51
2024-02-09target/riscv: move 'pmu-mask' and 'pmu-num' to riscv_cpu_properties[]Daniel Henrique Barboza1-7/+84
2024-02-09target/riscv: make riscv_cpu_is_vendor() publicDaniel Henrique Barboza1-0/+5
2024-02-09target/riscv: Add infrastructure for 'B' MISA extensionRob Bradford1-2/+3
2024-02-03target/riscv: Populate CPUClass.mmu_indexRichard Henderson1-0/+6
2024-01-10target/riscv: Ensure mideleg is set correctly on resetAlistair Francis1-0/+8
2024-01-10target/riscv: add rva22s64 cpuDaniel Henrique Barboza1-0/+8
2024-01-10target/riscv: add RVA22S64 profileDaniel Henrique Barboza1-0/+32
2024-01-10target/riscv: add 'parent' in profile descriptionDaniel Henrique Barboza1-0/+1
2024-01-10target/riscv: add satp_mode profile supportDaniel Henrique Barboza1-0/+1
2024-01-10target/riscv/cpu.c: add riscv_cpu_is_32bit()Daniel Henrique Barboza1-1/+6
2024-01-10target/riscv/cpu.c: finalize satp_mode earlierDaniel Henrique Barboza1-8/+8
2024-01-10target/riscv: add priv ver restriction to profilesDaniel Henrique Barboza1-0/+1
2024-01-10target/riscv: implement svadeDaniel Henrique Barboza1-0/+1
2024-01-10target/riscv: add 'rva22u64' CPUDaniel Henrique Barboza1-0/+17
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