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| author | Daniel Henrique Barboza <dbarboza@ventanamicro.com> | 2023-12-18 09:53:28 -0300 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2024-01-10 18:47:47 +1000 |
| commit | 1a7d4fcb3fe9d4215b3d6ead362af379a82c1c49 (patch) | |
| tree | 553c8390759fb0c16425fb34b6c18f2d991584c6 /target/riscv/cpu.c | |
| parent | 48531f5adb2aede5519d072b9bbc27f46994ce2d (diff) | |
| download | qemu-1a7d4fcb3fe9d4215b3d6ead362af379a82c1c49.zip qemu-1a7d4fcb3fe9d4215b3d6ead362af379a82c1c49.tar.gz qemu-1a7d4fcb3fe9d4215b3d6ead362af379a82c1c49.tar.bz2 | |
target/riscv: add priv ver restriction to profiles
Some profiles, like RVA22S64, has a priv_spec requirement.
Make this requirement explicit for all profiles. We'll validate this
requirement finalize() time and, in case the user chooses an
incompatible priv_spec while activating a profile, a warning will be
shown.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231218125334.37184-21-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/cpu.c')
| -rw-r--r-- | target/riscv/cpu.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0ec0d89..563fd4f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1536,6 +1536,7 @@ Property riscv_cpu_options[] = { static RISCVCPUProfile RVA22U64 = { .name = "rva22u64", .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVU, + .priv_spec = RISCV_PROFILE_ATTR_UNUSED, .ext_offsets = { CPU_CFG_OFFSET(ext_zicsr), CPU_CFG_OFFSET(ext_zihintpause), CPU_CFG_OFFSET(ext_zba), CPU_CFG_OFFSET(ext_zbb), |