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path: root/target/riscv/cpu.c
AgeCommit message (Expand)AuthorFilesLines
2022-09-07target/riscv: Add sscofpmf extension supportAtish Patra1-0/+12
2022-09-07target/riscv: Add stimecmp supportAtish Patra1-0/+9
2022-09-07target/riscv: Use official extension names for AIA CSRsAnup Patel1-5/+4
2022-09-07target/riscv: Add xicondops in ISA entryRahul Pathak1-0/+1
2022-09-07target/riscv: Add Zihintpause supportDao Lu1-0/+2
2022-09-07target/riscv: rvv: Add option 'rvv_ma_all_1s' to enable optional mask agnosti...eopXD1-0/+1
2022-09-07target/riscv: Fix checks in hmode/hmode32Weiwei Li1-0/+5
2022-09-07target/riscv: H extension depends on I extensionWeiwei Li1-0/+6
2022-09-07target/riscv: Add check for supported privilege mode combinationsWeiwei Li1-0/+6
2022-09-07target/riscv: move zmmul out of the experimental propertiesWeiwei Li1-1/+2
2022-09-07target/riscv: Force disable extensions if priv spec version does not matchAnup Patel1-56/+94
2022-07-27RISC-V: Allow both Zmmul and MPalmer Dabbelt1-5/+0
2022-07-03target/riscv: Don't force update priv spec version to latestAnup Patel1-4/+8
2022-07-03target/riscv: Ibex: Support priv version 1.11Alistair Francis1-1/+1
2022-07-03target/riscv: pmu: Make number of counters configurableAtish Patra1-2/+1
2022-07-03target/riscv: pmu: Rename the counters extension to pmuAtish Patra1-2/+2
2022-06-10target/riscv: Don't expose the CPU properties on names CPUsAlistair Francis1-11/+46
2022-06-10target/riscv: rvv: Add option 'rvv_ta_all_1s' to enable optional tail agnosti...eopXD1-0/+2
2022-06-10target/riscv: Wake on VS-level external interruptsAndrew Bresticker1-1/+1
2022-06-10target/riscv: add support for zmmul extension v0.1Weiwei Li1-0/+7
2022-05-24target/riscv: add zicsr/zifencei to isa_stringHongren (Zenithal) Zheng1-0/+2
2022-05-24target/riscv: Set [m|s]tval for both illegal and virtual instruction trapsAnup Patel1-0/+2
2022-05-24target/riscv: Fix typo of mimpid cpu optionFrank Chang1-2/+2
2022-05-24target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realizeWeiwei Li1-12/+12
2022-05-24target/riscv: Move/refactor ISA extension checksTsukasa OI1-15/+16
2022-05-24target/riscv: FP extension requirementsTsukasa OI1-0/+25
2022-05-24target/riscv: Change "G" expansionTsukasa OI1-2/+5
2022-05-24target/riscv: Disable "G" by defaultTsukasa OI1-1/+1
2022-05-24target/riscv: Fix coding style on "G" expansionTsukasa OI1-2/+2
2022-05-24target/riscv: Add short-isa-string optionTsukasa OI1-1/+5
2022-05-24target/riscv: Move Zhinx* extensions on ISA stringTsukasa OI1-2/+2
2022-04-29target/riscv: add scalar crypto related extenstion strings to isa_stringWeiwei Li1-0/+13
2022-04-29target/riscv: rvk: expose zbk* and zk* propertiesWeiwei Li1-0/+13
2022-04-29target/riscv: rvk: add cfg properties for zbk* and zk*Weiwei Li1-0/+23
2022-04-29target/riscv: Support configuarable marchid, mvendorid, mipid CSR valuesFrank Chang1-0/+9
2022-04-22target/riscv: cpu: Enable native debug featureBin Meng1-1/+1
2022-04-22target/riscv: csr: Hook debug CSR read/writeBin Meng1-0/+4
2022-04-22target/riscv: cpu: Add a config option for native debugBin Meng1-0/+5
2022-04-22target/riscv: debug: Implement debug related TCGCPUOpsBin Meng1-0/+3
2022-04-22target/riscv: Add isa extenstion strings to the device treeAtish Patra1-0/+60
2022-04-22target/riscv: misa to ISA string conversion fixTsukasa OI1-5/+5
2022-04-22target/riscv: Allow software access to MIP SEIPAlistair Francis1-1/+9
2022-04-22target/riscv: cpu: Fixup indentationAlistair Francis1-10/+10
2022-04-22target/riscv: Enable privileged spec version 1.12Atish Patra1-3/+5
2022-03-03target/riscv: expose zfinx, zdinx, zhinx{min} propertiesWeiwei Li1-0/+5
2022-03-03target/riscv: add cfg properties for zfinx, zdinx and zhinx{min}Weiwei Li1-0/+12
2022-02-16target/riscv: add support for svpbmt extensionWeiwei Li1-0/+1
2022-02-16target/riscv: add support for svinval extensionWeiwei Li1-0/+1
2022-02-16target/riscv: add support for svnapot extensionWeiwei Li1-0/+2
2022-02-16target/riscv: Allow users to force enable AIA CSRs in HARTAnup Patel1-0/+5
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