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cpu.c
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Author
Files
Lines
2021-02-05
cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass
Claudio Fontana
1
-7
/
+16
2021-02-05
cpu: move do_unaligned_access to tcg_ops
Claudio Fontana
1
-1
/
+1
2021-02-05
cpu: move cc->transaction_failed to tcg_ops
Claudio Fontana
1
-1
/
+1
2021-02-05
cpu: move cc->do_interrupt to tcg_ops
Claudio Fontana
1
-1
/
+1
2021-02-05
cpu: Move tlb_fill to tcg_ops
Eduardo Habkost
1
-1
/
+1
2021-02-05
cpu: Move cpu_exec_* to tcg_ops
Eduardo Habkost
1
-1
/
+1
2021-02-05
cpu: Move synchronize_from_tb() to tcg_ops
Eduardo Habkost
1
-1
/
+1
2021-02-05
target/riscv: remove CONFIG_TCG, as it is always TCG
Claudio Fontana
1
-2
/
+1
2021-02-05
cpu: Introduce TCGCpuOperations struct
Eduardo Habkost
1
-1
/
+1
2021-01-16
target/riscv: Generate the GDB XML file for CSR registers dynamically
Bin Meng
1
-0
/
+12
2021-01-16
gdb: riscv: Add target description
Sylvain Pelissier
1
-0
/
+13
2021-01-07
tcg: Make tb arg to synchronize_from_tb const
Richard Henderson
1
-1
/
+2
2020-12-17
target/riscv: cpu: Set XLEN independently from target
Alistair Francis
1
-9
/
+16
2020-12-17
target/riscv: cpu: Remove compile time XLEN checks
Alistair Francis
1
-9
/
+10
2020-12-17
target/riscv: Specify the XLEN for CPUs
Alistair Francis
1
-10
/
+23
2020-12-17
target/riscv: Add a riscv_cpu_is_32bit() helper function
Alistair Francis
1
-0
/
+9
2020-11-03
target/riscv: Add basic vmstate description of CPU
Yifei Jiang
1
-7
/
+1
2020-11-03
target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit
Yifei Jiang
1
-3
/
+5
2020-09-18
target/riscv: Set instance_align on RISCVCPU TypeInfo
Richard Henderson
1
-0
/
+1
2020-09-09
target/riscv: cpu: Set reset vector based on the configured property value
Bin Meng
1
-5
/
+2
2020-09-09
target/riscv: cpu: Add a new 'resetvec' property
Bin Meng
1
-0
/
+1
2020-09-09
target/riscv: Fix bug in getting trap cause name for trace_riscv_trap
Yifei Jiang
1
-0
/
+11
2020-07-02
target/riscv: configure and turn on vector extension from command line
LIU Zhiwei
1
-0
/
+43
2020-07-02
target/riscv: implementation-defined constant parameters
LIU Zhiwei
1
-0
/
+7
2020-06-19
hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004
Bin Meng
1
-8
/
+8
2020-06-19
target/riscv: Rename IBEX CPU init routine
Bin Meng
1
-2
/
+2
2020-06-19
riscv: Keep the CPU init routine names consistent
Bin Meng
1
-4
/
+4
2020-06-19
riscv: Generalize CPU init routine for the imacu CPU
Bin Meng
1
-21
/
+10
2020-06-19
riscv: Generalize CPU init routine for the gcsu CPU
Bin Meng
1
-14
/
+6
2020-06-19
riscv: Generalize CPU init routine for the base CPU
Bin Meng
1
-13
/
+5
2020-06-08
Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-5.1-pull-re...
Peter Maydell
1
-2
/
+4
2020-06-05
target/riscv/cpu: Restrict CPU migration to system-mode
Philippe Mathieu-Daudé
1
-2
/
+4
2020-06-03
target/riscv: Add the lowRISC Ibex CPU
Alistair Francis
1
-0
/
+10
2020-06-03
target/riscv: Don't set PMP feature in the cpu init
Alistair Francis
1
-5
/
+0
2020-06-03
target/riscv: Disable the MMU correctly
Alistair Francis
1
-2
/
+3
2020-06-03
target/riscv: Don't overwrite the reset vector
Alistair Francis
1
-1
/
+2
2020-06-03
target/riscv: Drop support for ISA spec version 1.09.1
Alistair Francis
1
-2
/
+0
2020-06-03
target/riscv: Remove the deprecated CPUs
Alistair Francis
1
-28
/
+0
2020-04-29
target/riscv: Add a sifive-e34 cpu type
Corey Wharton
1
-0
/
+10
2020-03-17
cpu: Use DeviceClass reset instead of a special CPUClass reset
Peter Maydell
1
-3
/
+4
2020-03-05
RISC-V: Add a missing "," in riscv_excp_names
Palmer Dabbelt
1
-2
/
+2
2020-02-27
target/riscv: Allow enabling the Hypervisor extension
Alistair Francis
1
-0
/
+5
2020-02-27
target/riscv: Add support for the 32-bit MSTATUSH CSR
Alistair Francis
1
-0
/
+3
2020-02-27
target/riscv: Dump Hypervisor registers if enabled
Alistair Francis
1
-0
/
+33
2020-02-27
target/riscv: Rename the H irqs to VS irqs
Alistair Francis
1
-3
/
+3
2020-02-27
target/riscv: Add support for the new execption numbers
Alistair Francis
1
-0
/
+8
2020-02-27
target/riscv: Convert MIP CSR to target_ulong
Alistair Francis
1
-1
/
+1
2020-01-24
qdev: set properties with device_class_set_props()
Marc-André Lureau
1
-1
/
+1
2020-01-24
cpu: Use cpu_class_set_parent_reset()
Greg Kurz
1
-2
/
+1
2019-11-14
target/riscv: Remove atomic accesses to MIP CSR
Alistair Francis
1
-3
/
+2
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