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path: root/target/riscv/cpu.c
AgeCommit message (Expand)AuthorFilesLines
2021-02-05cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClassClaudio Fontana1-7/+16
2021-02-05cpu: move do_unaligned_access to tcg_opsClaudio Fontana1-1/+1
2021-02-05cpu: move cc->transaction_failed to tcg_opsClaudio Fontana1-1/+1
2021-02-05cpu: move cc->do_interrupt to tcg_opsClaudio Fontana1-1/+1
2021-02-05cpu: Move tlb_fill to tcg_opsEduardo Habkost1-1/+1
2021-02-05cpu: Move cpu_exec_* to tcg_opsEduardo Habkost1-1/+1
2021-02-05cpu: Move synchronize_from_tb() to tcg_opsEduardo Habkost1-1/+1
2021-02-05target/riscv: remove CONFIG_TCG, as it is always TCGClaudio Fontana1-2/+1
2021-02-05cpu: Introduce TCGCpuOperations structEduardo Habkost1-1/+1
2021-01-16target/riscv: Generate the GDB XML file for CSR registers dynamicallyBin Meng1-0/+12
2021-01-16gdb: riscv: Add target descriptionSylvain Pelissier1-0/+13
2021-01-07tcg: Make tb arg to synchronize_from_tb constRichard Henderson1-1/+2
2020-12-17target/riscv: cpu: Set XLEN independently from targetAlistair Francis1-9/+16
2020-12-17target/riscv: cpu: Remove compile time XLEN checksAlistair Francis1-9/+10
2020-12-17target/riscv: Specify the XLEN for CPUsAlistair Francis1-10/+23
2020-12-17target/riscv: Add a riscv_cpu_is_32bit() helper functionAlistair Francis1-0/+9
2020-11-03target/riscv: Add basic vmstate description of CPUYifei Jiang1-7/+1
2020-11-03target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unitYifei Jiang1-3/+5
2020-09-18target/riscv: Set instance_align on RISCVCPU TypeInfoRichard Henderson1-0/+1
2020-09-09target/riscv: cpu: Set reset vector based on the configured property valueBin Meng1-5/+2
2020-09-09target/riscv: cpu: Add a new 'resetvec' propertyBin Meng1-0/+1
2020-09-09target/riscv: Fix bug in getting trap cause name for trace_riscv_trapYifei Jiang1-0/+11
2020-07-02target/riscv: configure and turn on vector extension from command lineLIU Zhiwei1-0/+43
2020-07-02target/riscv: implementation-defined constant parametersLIU Zhiwei1-0/+7
2020-06-19hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004Bin Meng1-8/+8
2020-06-19target/riscv: Rename IBEX CPU init routineBin Meng1-2/+2
2020-06-19riscv: Keep the CPU init routine names consistentBin Meng1-4/+4
2020-06-19riscv: Generalize CPU init routine for the imacu CPUBin Meng1-21/+10
2020-06-19riscv: Generalize CPU init routine for the gcsu CPUBin Meng1-14/+6
2020-06-19riscv: Generalize CPU init routine for the base CPUBin Meng1-13/+5
2020-06-08Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-5.1-pull-re...Peter Maydell1-2/+4
2020-06-05target/riscv/cpu: Restrict CPU migration to system-modePhilippe Mathieu-Daudé1-2/+4
2020-06-03target/riscv: Add the lowRISC Ibex CPUAlistair Francis1-0/+10
2020-06-03target/riscv: Don't set PMP feature in the cpu initAlistair Francis1-5/+0
2020-06-03target/riscv: Disable the MMU correctlyAlistair Francis1-2/+3
2020-06-03target/riscv: Don't overwrite the reset vectorAlistair Francis1-1/+2
2020-06-03target/riscv: Drop support for ISA spec version 1.09.1Alistair Francis1-2/+0
2020-06-03target/riscv: Remove the deprecated CPUsAlistair Francis1-28/+0
2020-04-29target/riscv: Add a sifive-e34 cpu typeCorey Wharton1-0/+10
2020-03-17cpu: Use DeviceClass reset instead of a special CPUClass resetPeter Maydell1-3/+4
2020-03-05RISC-V: Add a missing "," in riscv_excp_namesPalmer Dabbelt1-2/+2
2020-02-27target/riscv: Allow enabling the Hypervisor extensionAlistair Francis1-0/+5
2020-02-27target/riscv: Add support for the 32-bit MSTATUSH CSRAlistair Francis1-0/+3
2020-02-27target/riscv: Dump Hypervisor registers if enabledAlistair Francis1-0/+33
2020-02-27target/riscv: Rename the H irqs to VS irqsAlistair Francis1-3/+3
2020-02-27target/riscv: Add support for the new execption numbersAlistair Francis1-0/+8
2020-02-27target/riscv: Convert MIP CSR to target_ulongAlistair Francis1-1/+1
2020-01-24qdev: set properties with device_class_set_props()Marc-André Lureau1-1/+1
2020-01-24cpu: Use cpu_class_set_parent_reset()Greg Kurz1-2/+1
2019-11-14target/riscv: Remove atomic accesses to MIP CSRAlistair Francis1-3/+2
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