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path: root/target/riscv/cpu.c
AgeCommit message (Expand)AuthorFilesLines
2021-10-22target/riscv: line up all of the registers in the info register dumpTravis Geiselbrecht1-5/+5
2021-10-07target/riscv: Remove RVB (replaced by Zb[abcs])Philipp Tomsich1-26/+0
2021-10-07target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs propertiesPhilipp Tomsich1-0/+4
2021-09-21target/riscv: Expose interrupt pending bits as GPIO linesAlistair Francis1-0/+30
2021-09-21target/riscv: Update the ePMP CSR addressAlistair Francis1-0/+1
2021-09-14target/riscv: Restrict cpu_exec_interrupt() handler to sysemuPhilippe Mathieu-Daudé1-1/+1
2021-09-01target/riscv: Don't wrongly override isa versionLIU Zhiwei1-6/+8
2021-06-08target/riscv: rvb: add b-ext version cpu optionFrank Chang1-0/+23
2021-06-08target/riscv: rvb: support and turn on B-extension from command lineKito Cheng1-0/+4
2021-06-08target/riscv: Dump CSR mscratch/sscratch/satpChangbin Du1-2/+5
2021-06-08target/riscv: Remove unnecessary riscv_*_names[] declarationBin Meng1-2/+2
2021-05-26hw/core: Constify TCGCPUOpsRichard Henderson1-1/+1
2021-05-26cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOpsPhilippe Mathieu-Daudé1-1/+1
2021-05-26cpu: Move CPUClass::write_elf* to SysemuCPUOpsPhilippe Mathieu-Daudé1-2/+2
2021-05-26cpu: Move CPUClass::vmsd to SysemuCPUOpsPhilippe Mathieu-Daudé1-1/+1
2021-05-26cpu: Introduce SysemuCPUOps structurePhilippe Mathieu-Daudé1-0/+8
2021-05-26cpu: Rename CPUClass vmsd -> legacy_vmsdPhilippe Mathieu-Daudé1-2/+1
2021-05-11target/riscv: Remove the hardcoded RVXLEN macroAlistair Francis1-1/+5
2021-05-11target/riscv: fix a typo with interrupt namesEmmanuel Blot1-1/+1
2021-05-11target/riscv: Add ePMP support for the Ibex CPUAlistair Francis1-0/+1
2021-05-11target/riscv: Add a config option for ePMPHou Weiying1-0/+10
2021-05-11target/riscv: Convert the RISC-V exceptions to an enumAlistair Francis1-1/+1
2021-05-11target/riscv: Add Shakti C class CPUVijai Kumar K1-0/+1
2021-05-11target/riscv: Align the data type of reset vector addressDylan Jhong1-1/+1
2021-05-11target/riscv: Remove privilege v1.9 specific CSR related codeAtish Patra1-1/+1
2021-03-22target/riscv: Add proper two-stage lookup exception detectionGeorg Kotheimer1-0/+1
2021-03-09Various spelling fixesMichael Tokarev1-1/+1
2021-03-04target-riscv: support QMP dump-guest-memoryYifei Jiang1-0/+2
2021-02-05cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClassClaudio Fontana1-7/+16
2021-02-05cpu: move do_unaligned_access to tcg_opsClaudio Fontana1-1/+1
2021-02-05cpu: move cc->transaction_failed to tcg_opsClaudio Fontana1-1/+1
2021-02-05cpu: move cc->do_interrupt to tcg_opsClaudio Fontana1-1/+1
2021-02-05cpu: Move tlb_fill to tcg_opsEduardo Habkost1-1/+1
2021-02-05cpu: Move cpu_exec_* to tcg_opsEduardo Habkost1-1/+1
2021-02-05cpu: Move synchronize_from_tb() to tcg_opsEduardo Habkost1-1/+1
2021-02-05target/riscv: remove CONFIG_TCG, as it is always TCGClaudio Fontana1-2/+1
2021-02-05cpu: Introduce TCGCpuOperations structEduardo Habkost1-1/+1
2021-01-16target/riscv: Generate the GDB XML file for CSR registers dynamicallyBin Meng1-0/+12
2021-01-16gdb: riscv: Add target descriptionSylvain Pelissier1-0/+13
2021-01-07tcg: Make tb arg to synchronize_from_tb constRichard Henderson1-1/+2
2020-12-17target/riscv: cpu: Set XLEN independently from targetAlistair Francis1-9/+16
2020-12-17target/riscv: cpu: Remove compile time XLEN checksAlistair Francis1-9/+10
2020-12-17target/riscv: Specify the XLEN for CPUsAlistair Francis1-10/+23
2020-12-17target/riscv: Add a riscv_cpu_is_32bit() helper functionAlistair Francis1-0/+9
2020-11-03target/riscv: Add basic vmstate description of CPUYifei Jiang1-7/+1
2020-11-03target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unitYifei Jiang1-3/+5
2020-09-18target/riscv: Set instance_align on RISCVCPU TypeInfoRichard Henderson1-0/+1
2020-09-09target/riscv: cpu: Set reset vector based on the configured property valueBin Meng1-5/+2
2020-09-09target/riscv: cpu: Add a new 'resetvec' propertyBin Meng1-0/+1
2020-09-09target/riscv: Fix bug in getting trap cause name for trace_riscv_trapYifei Jiang1-0/+11
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