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cpu.c
Age
Commit message (
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Author
Files
Lines
2021-10-22
target/riscv: line up all of the registers in the info register dump
Travis Geiselbrecht
1
-5
/
+5
2021-10-07
target/riscv: Remove RVB (replaced by Zb[abcs])
Philipp Tomsich
1
-26
/
+0
2021-10-07
target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties
Philipp Tomsich
1
-0
/
+4
2021-09-21
target/riscv: Expose interrupt pending bits as GPIO lines
Alistair Francis
1
-0
/
+30
2021-09-21
target/riscv: Update the ePMP CSR address
Alistair Francis
1
-0
/
+1
2021-09-14
target/riscv: Restrict cpu_exec_interrupt() handler to sysemu
Philippe Mathieu-Daudé
1
-1
/
+1
2021-09-01
target/riscv: Don't wrongly override isa version
LIU Zhiwei
1
-6
/
+8
2021-06-08
target/riscv: rvb: add b-ext version cpu option
Frank Chang
1
-0
/
+23
2021-06-08
target/riscv: rvb: support and turn on B-extension from command line
Kito Cheng
1
-0
/
+4
2021-06-08
target/riscv: Dump CSR mscratch/sscratch/satp
Changbin Du
1
-2
/
+5
2021-06-08
target/riscv: Remove unnecessary riscv_*_names[] declaration
Bin Meng
1
-2
/
+2
2021-05-26
hw/core: Constify TCGCPUOps
Richard Henderson
1
-1
/
+1
2021-05-26
cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOps
Philippe Mathieu-Daudé
1
-1
/
+1
2021-05-26
cpu: Move CPUClass::write_elf* to SysemuCPUOps
Philippe Mathieu-Daudé
1
-2
/
+2
2021-05-26
cpu: Move CPUClass::vmsd to SysemuCPUOps
Philippe Mathieu-Daudé
1
-1
/
+1
2021-05-26
cpu: Introduce SysemuCPUOps structure
Philippe Mathieu-Daudé
1
-0
/
+8
2021-05-26
cpu: Rename CPUClass vmsd -> legacy_vmsd
Philippe Mathieu-Daudé
1
-2
/
+1
2021-05-11
target/riscv: Remove the hardcoded RVXLEN macro
Alistair Francis
1
-1
/
+5
2021-05-11
target/riscv: fix a typo with interrupt names
Emmanuel Blot
1
-1
/
+1
2021-05-11
target/riscv: Add ePMP support for the Ibex CPU
Alistair Francis
1
-0
/
+1
2021-05-11
target/riscv: Add a config option for ePMP
Hou Weiying
1
-0
/
+10
2021-05-11
target/riscv: Convert the RISC-V exceptions to an enum
Alistair Francis
1
-1
/
+1
2021-05-11
target/riscv: Add Shakti C class CPU
Vijai Kumar K
1
-0
/
+1
2021-05-11
target/riscv: Align the data type of reset vector address
Dylan Jhong
1
-1
/
+1
2021-05-11
target/riscv: Remove privilege v1.9 specific CSR related code
Atish Patra
1
-1
/
+1
2021-03-22
target/riscv: Add proper two-stage lookup exception detection
Georg Kotheimer
1
-0
/
+1
2021-03-09
Various spelling fixes
Michael Tokarev
1
-1
/
+1
2021-03-04
target-riscv: support QMP dump-guest-memory
Yifei Jiang
1
-0
/
+2
2021-02-05
cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass
Claudio Fontana
1
-7
/
+16
2021-02-05
cpu: move do_unaligned_access to tcg_ops
Claudio Fontana
1
-1
/
+1
2021-02-05
cpu: move cc->transaction_failed to tcg_ops
Claudio Fontana
1
-1
/
+1
2021-02-05
cpu: move cc->do_interrupt to tcg_ops
Claudio Fontana
1
-1
/
+1
2021-02-05
cpu: Move tlb_fill to tcg_ops
Eduardo Habkost
1
-1
/
+1
2021-02-05
cpu: Move cpu_exec_* to tcg_ops
Eduardo Habkost
1
-1
/
+1
2021-02-05
cpu: Move synchronize_from_tb() to tcg_ops
Eduardo Habkost
1
-1
/
+1
2021-02-05
target/riscv: remove CONFIG_TCG, as it is always TCG
Claudio Fontana
1
-2
/
+1
2021-02-05
cpu: Introduce TCGCpuOperations struct
Eduardo Habkost
1
-1
/
+1
2021-01-16
target/riscv: Generate the GDB XML file for CSR registers dynamically
Bin Meng
1
-0
/
+12
2021-01-16
gdb: riscv: Add target description
Sylvain Pelissier
1
-0
/
+13
2021-01-07
tcg: Make tb arg to synchronize_from_tb const
Richard Henderson
1
-1
/
+2
2020-12-17
target/riscv: cpu: Set XLEN independently from target
Alistair Francis
1
-9
/
+16
2020-12-17
target/riscv: cpu: Remove compile time XLEN checks
Alistair Francis
1
-9
/
+10
2020-12-17
target/riscv: Specify the XLEN for CPUs
Alistair Francis
1
-10
/
+23
2020-12-17
target/riscv: Add a riscv_cpu_is_32bit() helper function
Alistair Francis
1
-0
/
+9
2020-11-03
target/riscv: Add basic vmstate description of CPU
Yifei Jiang
1
-7
/
+1
2020-11-03
target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit
Yifei Jiang
1
-3
/
+5
2020-09-18
target/riscv: Set instance_align on RISCVCPU TypeInfo
Richard Henderson
1
-0
/
+1
2020-09-09
target/riscv: cpu: Set reset vector based on the configured property value
Bin Meng
1
-5
/
+2
2020-09-09
target/riscv: cpu: Add a new 'resetvec' property
Bin Meng
1
-0
/
+1
2020-09-09
target/riscv: Fix bug in getting trap cause name for trace_riscv_trap
Yifei Jiang
1
-0
/
+11
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