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2020-09-18qom: Remove module_obj_name parameter from OBJECT_DECLARE* macrosEduardo Habkost1-1/+1
2020-09-09Use OBJECT_DECLARE_TYPE where possibleEduardo Habkost1-4/+2
2020-09-09Use DECLARE_*CHECKER* macrosEduardo Habkost1-6/+2
2020-09-09Move QOM typedefs and add missing includesEduardo Habkost1-4/+7
2020-08-21meson: targetPaolo Bonzini4-17/+25
2020-08-21meson: rename included C source files to .c.incPaolo Bonzini3-5/+5
2020-05-19softfloat: Name compare relation enumRichard Henderson1-2/+2
2020-03-19Merge remote-tracking branch 'remotes/ehabkost/tags/x86-and-machine-pull-requ...Peter Maydell2-5/+5
2020-03-17cpu: Use DeviceClass reset instead of a special CPUClass resetPeter Maydell2-5/+5
2020-03-17gdbstub: extend GByteArray to read register helpersAlex Bennée2-2/+2
2020-01-24cpu: Use cpu_class_set_parent_reset()Greg Kurz1-2/+1
2020-01-17Merge remote-tracking branch 'remotes/rth/tags/pull-or1k-20200116' into stagingPeter Maydell1-1/+1
2020-01-16target/openrisc: Fix FPCSR mask to allow setting DZFStafford Horne1-1/+1
2020-01-15tcg: Search includes from the project root source directoryPhilippe Mathieu-Daudé1-1/+1
2019-10-28target/openrisc: fetch code with translator_ldEmilio G. Cota1-1/+1
2019-09-04target/openrisc: Update cpu "any" to v1.3Richard Henderson1-1/+1
2019-09-04target/openrisc: Implement l.adrpRichard Henderson3-0/+16
2019-09-04target/openrisc: Implement move to/from FPCSRRichard Henderson5-5/+38
2019-09-04target/openrisc: Implement unordered fp comparisonsRichard Henderson5-0/+145
2019-09-04target/openrisc: Add support for ORFPX64A32Richard Henderson6-3/+332
2019-09-04target/openrisc: Check CPUCFG_OF32S for float insnsRichard Henderson2-50/+36
2019-09-04target/openrisc: Fix lf.ftoi.sRichard Henderson1-1/+1
2019-09-04target/openrisc: Add VR2 and AVR special processor registersRichard Henderson3-6/+19
2019-09-04target/openrisc: Move VR, UPR, DMMCFGR, IMMCFGR to cpu initRichard Henderson3-13/+22
2019-09-04target/openrisc: Make VR and PPC read-onlyRichard Henderson2-12/+1
2019-09-04target/openrisc: Cache R0 in DisasContextRichard Henderson1-7/+12
2019-09-04target/openrisc: Replace cpu register array with a functionRichard Henderson1-97/+116
2019-09-04target/openrisc: Add DisasContext parameter to check_r0_writeRichard Henderson1-47/+49
2019-09-03tcg: TCGMemOp is now accelerator independent MemOpTony Nguyen1-2/+2
2019-08-21hw/core: Move cpu.c, cpu.h from qom/ to hw/core/Markus Armbruster1-1/+1
2019-08-16Include hw/boards.h a bit lessMarkus Armbruster1-1/+0
2019-08-16Include hw/hw.h exactly where neededMarkus Armbruster1-1/+0
2019-08-16migration: Move the VMStateDescription typedef to typedefs.hMarkus Armbruster1-1/+1
2019-07-05general: Replace global smp variables with smp machine propertiesLike Xu1-1/+5
2019-06-12Include qemu-common.h exactly where neededMarkus Armbruster9-9/+0
2019-06-10cpu: Remove CPU_COMMONRichard Henderson1-2/+0
2019-06-10cpu: Introduce CPUNegativeOffsetStateRichard Henderson1-1/+1
2019-06-10cpu: Introduce cpu_set_cpustate_pointersRichard Henderson1-2/+1
2019-06-10cpu: Move ENV_OFFSET to exec/gen-icount.hRichard Henderson1-1/+0
2019-06-10target/openrisc: Use env_cpu, env_archcpuRichard Henderson3-12/+6
2019-06-10cpu: Replace ENV_GET_CPU with env_cpuRichard Henderson1-2/+0
2019-06-10cpu: Define ArchCPURichard Henderson1-0/+1
2019-06-10cpu: Define CPUArchState with typedefRichard Henderson1-2/+2
2019-06-10tcg: Split out target/arch/cpu-param.hRichard Henderson2-11/+20
2019-05-10tcg: Use CPUClass::tlb_fill in cputlb.cRichard Henderson1-6/+0
2019-05-10target/openrisc: Convert to CPUClass::tlb_fillRichard Henderson3-36/+39
2019-05-08target/openrisc: Fix LGPL information in the file headersThomas Huth8-8/+8
2019-04-24tcg: Hoist max_insns computation to tb_gen_codeRichard Henderson1-2/+2
2019-04-18disas: Rename include/disas/bfd.h back to include/disas/dis-asm.hMarkus Armbruster1-1/+1
2019-04-18qom/cpu: Simplify how CPUClass:cpu_dump_state() printsMarkus Armbruster2-8/+6