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| author | Richard Henderson <richard.henderson@linaro.org> | 2019-05-06 13:00:06 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2019-09-04 12:48:12 -0700 |
| commit | d29f4368a71c6fe5de3a4424c67d4a3a2e577843 (patch) | |
| tree | 4ffbd040b3f9660db30502553143b02eb346361f /target/openrisc | |
| parent | 8bba7619b92a62aff537d295736ca5b871a89d3b (diff) | |
| download | qemu-d29f4368a71c6fe5de3a4424c67d4a3a2e577843.zip qemu-d29f4368a71c6fe5de3a4424c67d4a3a2e577843.tar.gz qemu-d29f4368a71c6fe5de3a4424c67d4a3a2e577843.tar.bz2 | |
target/openrisc: Cache R0 in DisasContext
Finish the race condition fix from the previous patch.
Reviewed-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/openrisc')
| -rw-r--r-- | target/openrisc/translate.c | 19 |
1 files changed, 12 insertions, 7 deletions
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index d635a46..341f923 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -48,6 +48,9 @@ typedef struct DisasContext { /* If not -1, jmp_pc contains this value and so is a direct jump. */ target_ulong jmp_pc_imm; + + /* The temporary corresponding to register 0 for this compilation. */ + TCGv R0; } DisasContext; static inline bool is_user(DisasContext *dc) @@ -64,7 +67,6 @@ static inline bool is_user(DisasContext *dc) static TCGv cpu_sr; static TCGv cpu_regs[32]; -static TCGv cpu_R0; static TCGv cpu_pc; static TCGv jmp_pc; /* l.jr/l.jalr temp pc */ static TCGv cpu_ppc; @@ -122,7 +124,6 @@ void openrisc_translate_init(void) shadow_gpr[0][i]), regnames[i]); } - cpu_R0 = cpu_regs[0]; } static void gen_exception(DisasContext *dc, unsigned int excp) @@ -165,7 +166,11 @@ static void check_ov64s(DisasContext *dc) static TCGv cpu_R(DisasContext *dc, int reg) { - return cpu_regs[reg]; + if (reg == 0) { + return dc->R0; + } else { + return cpu_regs[reg]; + } } /* @@ -175,7 +180,7 @@ static TCGv cpu_R(DisasContext *dc, int reg) static void check_r0_write(DisasContext *dc, int reg) { if (unlikely(reg == 0)) { - cpu_regs[0] = cpu_R0; + dc->R0 = cpu_regs[0]; } } @@ -747,7 +752,7 @@ static bool trans_l_swa(DisasContext *dc, arg_store *a) to cpu_regs[0]. Since l.swa is quite often immediately followed by a branch, don't bother reallocating; finish the TB using the "real" R0. This also takes care of RB input across the branch. */ - cpu_regs[0] = cpu_R0; + dc->R0 = cpu_regs[0]; lab_fail = gen_new_label(); lab_done = gen_new_label(); @@ -1292,9 +1297,9 @@ static void openrisc_tr_tb_start(DisasContextBase *db, CPUState *cs) /* Allow the TCG optimizer to see that R0 == 0, when it's true, which is the common case. */ if (dc->tb_flags & TB_FLAGS_R0_0) { - cpu_regs[0] = tcg_const_tl(0); + dc->R0 = tcg_const_tl(0); } else { - cpu_regs[0] = cpu_R0; + dc->R0 = cpu_regs[0]; } } |