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| author | Richard Henderson <richard.henderson@linaro.org> | 2019-08-25 14:28:37 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2019-09-04 12:48:22 -0700 |
| commit | b72e3ff65880f2b894a2692e2b0a14424058a919 (patch) | |
| tree | 3c019d506fe32b7f3af87821339291e57614746d /target/openrisc | |
| parent | d29f4368a71c6fe5de3a4424c67d4a3a2e577843 (diff) | |
| download | qemu-b72e3ff65880f2b894a2692e2b0a14424058a919.zip qemu-b72e3ff65880f2b894a2692e2b0a14424058a919.tar.gz qemu-b72e3ff65880f2b894a2692e2b0a14424058a919.tar.bz2 | |
target/openrisc: Make VR and PPC read-only
These SPRs are read-only. The writes can simply be ignored,
as we already do for other read-only (or missing) registers.
There is no reason to mask the value in env->vr.
Reviewed-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/openrisc')
| -rw-r--r-- | target/openrisc/cpu.h | 3 | ||||
| -rw-r--r-- | target/openrisc/sys_helper.c | 10 |
2 files changed, 1 insertions, 12 deletions
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 561f0f7..755282f 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -68,9 +68,6 @@ enum { (reg) |= ((v & 0x1f) << 2);\ } while (0) -/* Version Register */ -#define SPR_VR 0xFFFF003F - /* Interrupt */ #define NR_IRQS 32 diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index 1053409..d20f48b 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -39,10 +39,6 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) int idx; switch (spr) { - case TO_SPR(0, 0): /* VR */ - env->vr = rb; - break; - case TO_SPR(0, 11): /* EVBAR */ env->evbar = rb; break; @@ -62,10 +58,6 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) cpu_set_sr(env, rb); break; - case TO_SPR(0, 18): /* PPC */ - env->ppc = rb; - break; - case TO_SPR(0, 32): /* EPCR */ env->epcr = rb; break; @@ -204,7 +196,7 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd, switch (spr) { case TO_SPR(0, 0): /* VR */ - return env->vr & SPR_VR; + return env->vr; case TO_SPR(0, 1): /* UPR */ return env->upr; /* TT, DM, IM, UP present */ |