riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2021-05-02	target/mips: Move TCG source files under tcg/ sub directory	Philippe Mathieu-Daudé	25	-43/+41
2021-05-02	target/mips: Move CP0 helpers to sysemu/cp0.c	Philippe Mathieu-Daudé	4	-107/+129
2021-05-02	target/mips: Move exception management code to exception.c	Philippe Mathieu-Daudé	6	-163/+182
2021-05-02	target/mips: Move TLB management helpers to tcg/sysemu/tlb_helper.c	Philippe Mathieu-Daudé	5	-350/+340
2021-05-02	target/mips: Move helper_cache() to tcg/sysemu/special_helper.c	Philippe Mathieu-Daudé	5	-37/+47
2021-05-02	target/mips: Move Special opcodes to tcg/sysemu/special_helper.c	Philippe Mathieu-Daudé	7	-122/+151
2021-05-02	target/mips: Restrict CPUMIPSTLBContext::map_address() handlers scope	Philippe Mathieu-Daudé	2	-12/+7
2021-05-02	target/mips: Move tlb_helper.c to tcg/sysemu/	Philippe Mathieu-Daudé	5	-9/+6
2021-05-02	target/mips: Restrict mmu_init() to TCG	Philippe Mathieu-Daudé	3	-4/+3
2021-05-02	target/mips: Move sysemu TCG-specific code to tcg/sysemu/ subfolder	Philippe Mathieu-Daudé	7	-167/+179
2021-05-02	target/mips: Restrict cpu_mips_get_random() / update_pagemask() to TCG	Philippe Mathieu-Daudé	2	-4/+9
2021-05-02	target/mips: Move physical addressing code to sysemu/physaddr.c	Philippe Mathieu-Daudé	4	-255/+282
2021-05-02	target/mips: Move sysemu specific files under sysemu/ subfolder	Philippe Mathieu-Daudé	5	-6/+11
2021-05-02	target/mips: Move cpu_signal_handler definition around	Philippe Mathieu-Daudé	1	-5/+4
2021-05-02	target/mips: Add simple user-mode mips_cpu_tlb_fill()	Philippe Mathieu-Daudé	2	-10/+36
2021-05-02	target/mips: Add simple user-mode mips_cpu_do_interrupt()	Philippe Mathieu-Daudé	5	-5/+39
2021-05-02	target/mips: Introduce tcg-internal.h for TCG specific declarations	Philippe Mathieu-Daudé	2	-4/+23
2021-05-02	target/mips: Extract load/store helpers to ldst_helper.c	Philippe Mathieu-Daudé	3	-259/+289
2021-05-02	target/mips: Merge do_translate_address into cpu_mips_translate_address	Philippe Mathieu-Daudé	3	-24/+9
2021-05-02	target/mips: Declare mips_env_set_pc() inlined in "internal.h"	Philippe Mathieu-Daudé	3	-20/+14
2021-05-02	target/mips: Turn printfpr() macro into a proper function	Philippe Mathieu-Daudé	1	-27/+23
2021-05-02	target/mips: Restrict mips_cpu_dump_state() to cpu.c	Philippe Mathieu-Daudé	3	-78/+77
2021-05-02	target/mips: Optimize CPU/FPU regnames[] arrays	Philippe Mathieu-Daudé	3	-4/+4
2021-05-02	target/mips: Make CPU/FPU regnames[] arrays global	Philippe Mathieu-Daudé	4	-14/+17
2021-05-02	target/mips: Move msa_reset() to new source file	Philippe Mathieu-Daudé	3	-36/+61
2021-05-02	target/mips: Move IEEE rounding mode array to new source file	Philippe Mathieu-Daudé	3	-8/+19
2021-05-02	target/mips: Simplify meson TCG rules	Philippe Mathieu-Daudé	1	-3/+2
2021-05-02	target/mips: Make check_cp0_enabled() return a boolean	Philippe Mathieu-Daudé	2	-2/+9
2021-05-02	target/mips: Migrate missing CPU fields	Philippe Mathieu-Daudé	1	-6/+15
2021-05-02	target/mips: Remove spurious LOG_UNIMP of MTHC0 opcode	Philippe Mathieu-Daudé	1	-0/+1
2021-05-02	target/mips: Add missing CP0 check to nanoMIPS RDPGPR / WRPGPR opcodes	Philippe Mathieu-Daudé	1	-0/+2
2021-05-02	target/mips: Fix CACHEE opcode (CACHE using EVA addressing)	Philippe Mathieu-Daudé	1	-1/+3
2021-04-20	target/mips/rel6_translate: Change license to GNU LGPL v2.1 (or later)	Philippe Mathieu-Daudé	1	-5/+4
2021-04-13	target/mips: Fix TCG temporary leak in gen_cache_operation()	Philippe Mathieu-Daudé	1	-0/+2
2021-03-22	target/mips/mxu_translate.c: Fix array overrun for D16MIN/D16MAX	Peter Maydell	1	-4/+4
2021-03-13	target/mips/tx79: Salvage instructions description comment	Philippe Mathieu-Daudé	2	-160/+188
2021-03-13	target/mips: Remove 'C790 Multimedia Instructions' dead code	Philippe Mathieu-Daudé	1	-371/+0
2021-03-13	target/mips/tx79: Move PCPYLD / PCPYUD opcodes to decodetree	Philippe Mathieu-Daudé	3	-80/+48
2021-03-13	target/mips/tx79: Move PCPYH opcode to decodetree	Philippe Mathieu-Daudé	3	-39/+27
2021-03-13	target/mips/translate: Simplify PCPYH using deposit_i64()	Philippe Mathieu-Daudé	1	-30/+4
2021-03-13	target/mips/translate: Make gen_rdhwr() public	Philippe Mathieu-Daudé	2	-1/+3
2021-03-13	target/mips/tx79: Move MTHI1 / MTLO1 opcodes to decodetree	Philippe Mathieu-Daudé	3	-25/+17
2021-03-13	target/mips/tx79: Move MFHI1 / MFLO1 opcodes to decodetree	Philippe Mathieu-Daudé	6	-12/+94
2021-03-13	target/mips: Use gen_load_gpr[_hi]() when possible	Philippe Mathieu-Daudé	1	-23/+6
2021-03-13	target/mips: Extract MXU code to new mxu_translate.c file	Philippe Mathieu-Daudé	3	-1605/+1613
2021-03-13	target/mips: Introduce mxu_translate_init() helper	Philippe Mathieu-Daudé	2	-12/+17
2021-03-13	target/mips: Simplify decode_opc_mxu() ifdef'ry	Philippe Mathieu-Daudé	2	-4/+5
2021-03-13	target/mips: Convert decode_ase_mxu() to decodetree prototype	Philippe Mathieu-Daudé	1	-3/+5
2021-03-13	target/mips: Rename decode_opc_mxu() as decode_ase_mxu()	Philippe Mathieu-Daudé	1	-2/+2
2021-03-13	target/mips: Move MUL opcode check from decode_mxu() to decode_legacy()	Philippe Mathieu-Daudé	1	-14/+5