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| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-02-14 17:20:19 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-03-13 23:43:11 +0100 |
| commit | 1f9408d5502c877ddf91ce00f529488c4b5c98d5 (patch) | |
| tree | fe424fe99653b7cfccbd3b43df02798610bc1a62 /target/mips | |
| parent | ffc672aa977131ccfccfd0c2aee2b004adb69ed5 (diff) | |
| download | qemu-1f9408d5502c877ddf91ce00f529488c4b5c98d5.zip qemu-1f9408d5502c877ddf91ce00f529488c4b5c98d5.tar.gz qemu-1f9408d5502c877ddf91ce00f529488c4b5c98d5.tar.bz2 | |
target/mips/tx79: Move MTHI1 / MTLO1 opcodes to decodetree
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210214175912.732946-10-f4bug@amsat.org>
Diffstat (limited to 'target/mips')
| -rw-r--r-- | target/mips/translate.c | 25 | ||||
| -rw-r--r-- | target/mips/tx79.decode | 3 | ||||
| -rw-r--r-- | target/mips/tx79_translate.c | 14 |
3 files changed, 17 insertions, 25 deletions
diff --git a/target/mips/translate.c b/target/mips/translate.c index 889c896..256e295 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1360,8 +1360,6 @@ enum { MMI_OPC_PLZCW = 0x04 | MMI_OPC_CLASS_MMI, MMI_OPC_CLASS_MMI0 = 0x08 | MMI_OPC_CLASS_MMI, MMI_OPC_CLASS_MMI2 = 0x09 | MMI_OPC_CLASS_MMI, - MMI_OPC_MTHI1 = 0x11 | MMI_OPC_CLASS_MMI, /* Same minor as OPC_MTHI */ - MMI_OPC_MTLO1 = 0x13 | MMI_OPC_CLASS_MMI, /* Same minor as OPC_MTLO */ MMI_OPC_MULT1 = 0x18 | MMI_OPC_CLASS_MMI, /* Same minor as OPC_MULT */ MMI_OPC_MULTU1 = 0x19 | MMI_OPC_CLASS_MMI, /* Same min. as OPC_MULTU */ MMI_OPC_DIV1 = 0x1A | MMI_OPC_CLASS_MMI, /* Same minor as OPC_DIV */ @@ -3462,25 +3460,6 @@ static void gen_shift(DisasContext *ctx, uint32_t opc, tcg_temp_free(t1); } -#if defined(TARGET_MIPS64) -/* Copy GPR to and from TX79 HI1/LO1 register. */ -static void gen_HILO1_tx79(DisasContext *ctx, uint32_t opc, int reg) -{ - switch (opc) { - case MMI_OPC_MTHI1: - gen_load_gpr(cpu_HI[1], reg); - break; - case MMI_OPC_MTLO1: - gen_load_gpr(cpu_LO[1], reg); - break; - default: - MIPS_INVAL("mfthilo1 TX79"); - gen_reserved_instruction(ctx); - break; - } -} -#endif - /* Arithmetic on HI/LO registers */ static void gen_HILO(DisasContext *ctx, uint32_t opc, int acc, int reg) { @@ -25108,10 +25087,6 @@ static void decode_mmi(CPUMIPSState *env, DisasContext *ctx) case MMI_OPC_DIVU1: gen_div1_tx79(ctx, opc, rs, rt); break; - case MMI_OPC_MTLO1: - case MMI_OPC_MTHI1: - gen_HILO1_tx79(ctx, opc, rs); - break; case MMI_OPC_PLZCW: /* TODO: MMI_OPC_PLZCW */ case MMI_OPC_PMFHL: /* TODO: MMI_OPC_PMFHL */ case MMI_OPC_PMTHL: /* TODO: MMI_OPC_PMTHL */ diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode index 2e287eb..30737da 100644 --- a/target/mips/tx79.decode +++ b/target/mips/tx79.decode @@ -17,9 +17,12 @@ # Named instruction formats. These are generally used to # reduce the amount of duplication between instruction patterns. +@rs ...... rs:5 ..... .......... ...... &rtype rt=0 rd=0 sa=0 @rd ...... .......... rd:5 ..... ...... &rtype rs=0 rt=0 sa=0 ########################################################################### MFHI1 011100 0000000000 ..... 00000 010000 @rd +MTHI1 011100 ..... 0000000000 00000 010001 @rs MFLO1 011100 0000000000 ..... 00000 010010 @rd +MTLO1 011100 ..... 0000000000 00000 010011 @rs diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c index 22bd603..905245c 100644 --- a/target/mips/tx79_translate.c +++ b/target/mips/tx79_translate.c @@ -35,3 +35,17 @@ static bool trans_MFLO1(DisasContext *ctx, arg_rtype *a) return true; } + +static bool trans_MTHI1(DisasContext *ctx, arg_rtype *a) +{ + gen_load_gpr(cpu_HI[1], a->rs); + + return true; +} + +static bool trans_MTLO1(DisasContext *ctx, arg_rtype *a) +{ + gen_load_gpr(cpu_LO[1], a->rs); + + return true; +} |